基于FPGA的千兆以太网端口通信设计

doi:10.16180/j.cnki.issn1007-7820.2024.01.007

摘要/Abstract

摘要：

针对嵌入式领域中以太网传输速率以及实时性问题,文中提出了一种基于FPGA(Field Programmable Gate Array)的千兆以太网端口通信的设计方案。设计了千兆以太网交换机的转发功能,基于标签转发实现了端对端数据通信。CPU(Central Processing Unit)发出带有标签的数据报文,通过千兆网口输出数据报文,经过RGMII(Reduced Gigabit Media Independent Interface)接口将带标签的数据报文发送给FPGA,FPGA通过内部逻辑判断标签中的输出端口号域并去除标签,从相应千兆网口向连接设备输出数据报文。外设通过千兆网端口输入数据报文,通过SGMII(Serial Gigabit Media Independent Interface)协议将数据报文发送给FPGA,FPGA通过内部逻辑添加标签并轮询输出给CPU,从而实现多个千兆网口连接设备互通。实验结果验证了FPGA逻辑的可行性和有效性,传输速率达到1 Gbit·s^-1,报文转发延时小于100 μs,报文丢包率为0%,数据传输稳定性较高,满足现有项目的实际需求。

关键词: FPGA, 千兆以太网, 以太网交换机, 标签, CPU, 数据报文, RGMII接口, SGMII协议

Abstract:

In view of the problem of Ethernet transmission rate and real-time in embedded field, a design of Gigabit Ethernet port communication based on FPGA(Field Programmable Gate Array)is proposed. This study designs the forwarding function of Gigabit Ethernet switch, and implements end-to-end data communication based on label forwarding. Datagrams with label are sent by CPU(Central Processing Unit), and are outputted through Gigabit Ethernet interface, and are sent to FPGA through RGMII(Reduced Gigabit Media Independent Interface)port. FPGA judges output port number field in label through internal logic and removes label, and outputs datagrams to connecting device from corresponding Gigabit Ethernet interface. Peripherals input datagrams through Gigabit Ethernet ports, and send datagrams to FPGA through SGMII(Serial Gigabit Media Independent Interface) protocol. FPGA adds labels through internal logic and outputs them to CPU through polling, so as to realize interworking of connecting devices of multiple Gigabit Ethernet interface. The experimental results reveal the feasibility and effectiveness of the FPGA logic. The transmission rate reaches 1 Gbit·s^-1, the datagrams forwarding delay is less than 100 μs, and the packet loss rate is 0%,which indicates that the data transmission stability is high, and the proposed design meets the actual needs of existing projects.

Key words: FPGA, Gigabit Ethernet, ethernet switch, label, CPU, datagram, RGMII interface, SGMII protocol

中图分类号:

TN79

兰唯,韩延喆,扈啸. 基于FPGA的千兆以太网端口通信设计[J]. 电子科技, 2024, 37(1): 48-54.

LAN Wei,HAN Yanzhe,HU Xiao. Design of Gigabit Ethernet Port Communication Based on FPGA[J]. Electronic Science and Technology, 2024, 37(1): 48-54.

图/表 14

图1

图2

图3

图4

图5

图6

图7

图8

表1

图9

表2

表3

表4

表5

参考文献 18

[1]	李辉, 景浩, 严康华, 等. 基于卷积循环网络与非局部模块的语音增强方法[J]. 电子科技, 2022, 35(3):8-15.
	Li Hui, Jing Hao, Yan Kanghua, et al. Speech enhancement method based on convolutional recurrent network and non-local module[J]. Electronic Science and Technology, 2022, 35(3):8-15.
[2]	何宁, 薛庆军, 程勇. 基于TCP/IP协议的嵌入式网络系统的设计与应用[J]. 山东科技大学学报(自然科学版), 2004, 23(1):55-57.
	He Ning, Xue Qingjun, Cheng Yong. Design and apllication of embedded network system based on TCP/IP[J]. Journal of Shandong University of Science and Technology(Natural Science), 2004, 23(1):55-57.
[3]	葛永明, 林继宝. 嵌入式系统以太网接口的设计[J]. 电子技术应用, 2002(3):25-27.
	Ge Yongming, Lin Jibao. Design of ethernet interface for embedded system[J]. Application of Electronic Technique, 2002(3):25-27.
[4]	程耕国, 高厚礼. 基于TCP/IP协议单片机上网的设计与实现[J]. 武汉科技大学学报, 2004, 27(2):174-175,197.
	Cheng Gengguo, Gao Houli. TCP/IP-protocol-based connection of single-chip with internet:Design and realization[J]. Journal of Wuhan University of Science and Technology, 2004, 27(2):174-175,197.
[5]	Hwang S, Abraham J A. Test data compression and test time reduction using an embedded microprocessor[J]. IEEE Transactions on Very Large Scale Integration Systems, 2003, 11(5):853-862. doi: 10.1109/TVLSI.2003.817140
[6]	杨振雷, 刘承敏, 青先国, 等. 基于Zynq-7000的千兆以太网传输系统设计与实现[J]. 核技术, 2021, 44(2):1-8.
	Yang Zhenlei, Liu Chengmin, Qing Xianguo, et al. Design and implementation of Gigabit Ethernet transmission system based on Zynq-700[J]. Nuclear Techniques, 2021, 44(2):1-8.
[7]	樊光辉, 孙国强, 向健勇. 基于千兆以太网技术的大型实时传输系统[J]. 电子科技, 2009, 22(3):37-40.
	Fan Guanghui, Sun Guoqiang, Xiang Jianyong. Large-scale real-time transmission system based on Gigabit Ethernet technology[J]. Electronic Science and Technology, 2009, 22(3):37-40.
[8]	朱佳. 千兆以太网的SerDes接口电路设计[D]. 无锡: 江南大学, 2021:27-55.
	Zhu Jia. SerDes interface circuit design of Gigabit Ethernet[D]. Wuxi: Jiangnan University, 2021:27-55.
[9]	李岚, 苏敏, 程丽彬, 等. 基于FPGA多接口的千兆以太网IP核设计[J]. 电子信息对抗技术, 2020, 35(2):82-88.
	Li Lan, Su Min, Cheng Libin, et al. The Giabit Ethernet IP core designing based on FPGA of multi-interface[J]. Electronic Information Warfare Technology, 2020, 35(2):82-88.
[10]	王飞. 基于FPGA的点对点以太网接口设计实现[D]. 西安: 西安电子科技大学, 2011:22-49.
	Wang Fei. Design & implementation of an Ethernet interface for point-to-point transmission based on FPGA[D]. Xi'an: Xidian University, 2011:22-49.
[11]	韩冰. 基于千兆以太网的接口转换模块的设计与实现[D]. 太原: 中北大学, 2022:19-37.
	Han Bing. Design and implementation of interface conversion module based on Gigabit Ethernet[D]. Taiyuan: Central North University, 2022:19-37.
[12]	李鹏启, 李娟亚, 代波, 等. 一种基于DSP+FPGA的多路串口和以太网通信系统[J]. 兵工自动化, 2020, 39(8):1-3.
	Li Pengqi, Li Juanya, Dai Bo, et al. A multiplex serial port and ethernet communication system based on DSP+FPGA[J]. Ordnance Industry Automation, 2020, 39(8):1-3.
[13]	武建诚, 吴国东, 王志军, 等. 基于FPGA+ARM的冲击波超压测试系统[J]. 探测与控制学报, 2022, 44(2):92-96.
	Wu Jiancheng, Wu Guodong, Wang Zhijun, et al. Shock wave overpressure test system based on FPGA+ARM[J]. Journal of Detection & Control, 2022, 44(2):92-96.
[14]	周尧. 基于FPGA的千兆以太网采集传输设计[J]. 声学与电子工程, 2021, 142(2):52-55.
	Zhou Yao. Design of Gigabit Ethernet data acquisition and transmission based on FPGA[J]. Acoustics and Electronics Engineering, 2021, 142(2):52-55.
[15]	郑瑞, 肖顺文, 王涌. 基于FPGA的千兆以太网实时图像采集与传输系统设计[J]. 西华师范大学学报(自然科学版), 2022, 43(3):349-364.
	Zheng Rui, Xiao Shunwen, Wang Yong. Design of Gigabit Ethernet real time image acquisition and transmission system based on FPGA[J]. Journal of China West Normal University(Natural Sciences), 2022, 43(3):349-364.
[16]	古月, 姜威, 刘跃泽, 等. 基于ZYNQ的千兆以太网数据记录器设计[J]. 测控技术, 2022, 41(5):94-99.
	Gu Yue, Jiang Wei, Liu Yueze, et al. Gigabit Ethernet data acquisition system based on ZYNQ[J]. Measurement & Control Technology, 2022, 41(5):94-99.
[17]	张少芳, 李献军, 王月春, 等. 基于千兆以太网的弹载数据采集系统设计[J]. 兵器装备工程学报, 2020, 41(11):257-260.
	Zhang Shaofang, Li Xianjun, Wang Yuechun, et al. Designing missile storage data recorder based on Gigabit Ethernet[J]. Journal of Ordnance Equipment Engineering, 2020, 41(11):257-260.
[18]	林琦. 网络处理器协处理器验证平台设计与实现[D]. 长沙: 国防科学技术大学, 2013:37-66.
	Lin Qi. Design and implementation of the verification platform for NP coprocessors[D]. Changsha: National University of Defense Technology, 2013:37-66.

报文长度	报文流	测试仪发送端口	发送计数	测试仪接收端口	接收计数
64 Byte	1	Port1	43 940 420	Port1	43 940 420
64 Byte	2	Port2	43 952 750	Port2	43 952 750
128 Byte	1	Port1	25 360 198	Port1	25 360 198
128 Byte	2	Port2	25 367 404	Port2	25 367 404
256 Byte	1	Port1	13 557 633	Port1	13 557 633
256 Byte	2	Port2	13 561 408	Port2	13 561 408
512 Byte	1	Port1	7 072 744	Port1	7 072 744
512 Byte	2	Port2	7 074 867	Port2	7 074 867
1 024 Byte	1	Port1	3 602 208	Port1	3 602 208
1 024 Byte	2	Port2	3 603 231	Port2	3 603 231
1 518 Byte	1	Port1	2 465 186	Port1	2 465 186
1 518 Byte	2	Port2	2 465 862	Port2	2 465 862
64~1 518 Byte	1	Port1	4 628 442	Port1	4 628 442
64~1 518 Byte	2	Port2	4 629 743	Port2	4 629 743

报文长度	报文流	测试仪发送端口	发送计数	测试仪接收端口	接收计数
64 Byte	1	Port1	44 180 999	Port1	44 180 999
64 Byte	2	Port2	44 193 895	Port2	44 193 895
128 Byte	1	Port1	250 861 16	Port1	25 086 116
128 Byte	2	Port2	25 112 629	Port2	25 112 629
256 Byte	1	Port1	13 619 989	Port1	13 619 989
256 Byte	2	Port2	13 624 174	Port2	13 624 174
512 Byte	1	Port1	7 087 625	Port1	7 087 625
512 Byte	2	Port2	7 095 127	Port2	7 095 127
1 024 Byte	1	Port1	3 632 905	Port1	3 632 905
1 024 Byte	2	Port2	3 634 170	Port2	3 634 170
1 518 Byte	1	Port1	2 447 469	Port1	2 447 469
1 518 Byte	2	Port2	2 448 281	Port2	2 448 281
64~1 518 Byte	1	Port1	4 589 117	Port1	4 589 117
64~1 518 Byte	2	Port2	4 590 811	Port2	4 590 811

报文长度	报文流	Average /μs	Min /μs	Max /μs
256 Byte	1	5.329	5.26	5.38
512 Byte	1	8.414	8.34	8.46
1 024 Byte	1	14.542	14.48	14.60
1 518 Byte	1	20.473	20.40	20.54
256~1 518 Byte	1	20.241	5.32	21.34

报文长度	报文流	测试仪发送端口	发送计数	测试仪接收端口	接收计数
256 Byte	1	Port1	13 619 989	Port1	13 619 989
256 Byte	2	Port2	13 624 174	Port2	13 624 174
512 Byte	1	Port1	7 087 625	Port1	7 087 625
512 Byte	2	Port2	7 095 127	Port2	7 095 127
1 024 Byte	1	Port1	3 632 905	Port1	3 632 905
1 024 Byte	2	Port2	3 634 170	Port2	3 634 170
1 518 Byte	1	Port1	2 447 469	Port1	2 447 469
1 518 Byte	2	Port2	2 448 281	Port2	2 448 281
256~1 518	1	Port1	4 165 308	Port1	4 165 308
Byte	2	Port2	4 167 222	Port2	4 167 222