西安电子科技大学学报 ›› 2022, Vol. 49 ›› Issue (3): 206-212.doi: 10.19665/j.issn1001-2400.2022.03.023

• 电子科学与技术&其他 • 上一篇    下一篇

氮钝化对SiC MOS电容栅介质可靠性的影响

白志强1(),张艺蒙1,2(),汤晓燕1(),宋庆文1,2(),张玉明1(),戴小平3(),高秀秀3(),齐放3()   

  1. 1.西安电子科技大学 微电子学院,陕西 西安 710071
    2.西安电子科技大学 芜湖研究院,安徽 芜湖 241000
    3.湖南国芯半导体科技有限公司,湖南 株洲 412000
  • 收稿日期:2021-01-25 修回日期:2021-11-23 出版日期:2022-06-20 发布日期:2022-07-04
  • 通讯作者: 汤晓燕
  • 作者简介:白志强(1994—),男,西安电子科技大学博士研究生,E-mail: zhi_qiang_bai@163.com|张艺蒙(1982—),男,教授,博士,E-mail: zhangyimeng@xidian.edu.cn|宋庆文(1983—),男,教授,博士,E-mail: qwsong@xidian.edu.cn|张玉明(1965—),男,教授,博士,E-mail: zhangym@xidian.edu.cn|戴小平(1968—),男,高级工程师,E-mail: daixp@csrzic.com|高秀秀(1990—),女,工程师,硕士,E-mail: gaoxx10@csrzic.com|齐放(1984—),男,高级工程师,E-mail: qifang@csrzic.com
  • 基金资助:
    “功率半导体国家制造业创新中心建设”项目(2018XK2202);科学挑战专题项目(TZ2018003);陕西省重点研发项目(2018ZDL-GY01-03);陕西省重点研发项目(2020ZDLGY03-07);陕西省重点研发项目(2019GY-004);芜湖-西电产学研专项资金(XWYCXY-012020002)

The effect of nitrogen passivation on gate dielectric reliability of SiC MOS capacitors

BAI Zhiqiang1(),ZHANG Yimeng1,2(),TANG Xiaoyan1(),SONG Qingwen1,2(),ZHANG Yuming1(),DAI Xiaoping3(),GAO Xiuxiu3(),QI Fang3()   

  1. 1. School of Electronic Engineering,Xidian University,Xi’an 710071,China
    2. Xidian-Wuhu Research Institute,Wuhu 241000,China
    3. Coresing Semiconductor Technology Co.Ltd,Zhuzhou 412000,China
  • Received:2021-01-25 Revised:2021-11-23 Online:2022-06-20 Published:2022-07-04
  • Contact: Xiaoyan TANG

摘要:

一氧化氮退火是目前业内界面钝化的主流工艺,而钝化效果与一氧化氮退火的条件密切相关,因此选取合适的退火条件提高界面质量显得尤为重要。利用n型和p型碳化硅MOS电容研究了不同一氧化氮钝化时间对栅氧界面附近陷阱和栅介质可靠性的影响。通过平行电导峰测试、电容-电压回滞测试、栅偏应力测试和栅漏电测试,分别对界面陷阱、近界面陷阱、氧化层陷阱和栅介质可靠性进行了表征。结果显示,增加一氧化氮退火时间能够减少n型MOS电容的界面电子陷阱密度,提高界面质量。同时,增加一氧化氮退火时间可以减少影响阈值电压正向漂移的近界面电子陷阱,但会引入多余的近界面空穴陷阱,从而在改善器件阈值电压正向稳定性的同时会恶化阈值电压的负向稳定性。类似地,增加一氧化氮退火时间会减小氧化层中显负电性的有效固定电荷密度,但会增加氧化层中显正电性的有效固定电荷密度。栅漏电特性测试结果表明,一氧化氮退火时间对器件开态和关态工作条件下栅氧可靠性会产生不同的影响。研究结果为改善碳化硅MOSFET器件性能提供了有益的退火工艺参考。

关键词: 碳化硅, MOS电容, 界面态, 退火, 栅介质

Abstract:

Nitric oxide annealing is currently the mainstream interface passivation process in industry,and the passivation effect is severely affected by the annealing conditions of the nitric oxide,so it is important to select appropriate annealing conditions to improve the interface quality.In this paper,the influences of different nitric oxide passivation time on the traps near gate oxide interface and the reliability of gate dielectrics are investigated by the use of n-type and p-type SiC MOS capacitors.The interface traps,near-interface traps,oxide traps and the reliability of gate dielectrics are characterized by the parallel conductance peak test,capacitance-voltage hysteresis test,gate bias stress test and gate leakage test,respectively.The results show that increasing the nitric oxide annealing time can reduce the interface electron trap density of the n-type MOS capacitor and improve the interface quality.In addition,increasing the nitric oxide annealing time can reduce the near-interface electron traps that affect the positive shift of the threshold voltage,but at the same time it will introduce excess hole traps,which can improve the threshold voltage positive stability and worsen the threshold voltage negative stability.Similarly,increasing the nitric oxide annealing time will reduce the effective fixed charge density that is negatively charged in the oxide layer,but will increase the effective fixed charge density that is positively charged in the oxide layer.The results of gate leakage characteristics show that the nitric oxide annealed time has different effects on the gate oxide reliability during the on-state and off-state operation of the device.The results in this paper provide a useful annealing process reference for improving the performance of SiC MOSFETs.

Key words: silicon carbide, MOS capacitors, interface states, annealing, gate dielectrics

中图分类号: 

  • TN386
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