抗电磁侧信道攻击随机预混淆逻辑单元设计

doi:10.19665/j.issn1001-2400.2022.04.019

西安电子科技大学学报 ›› 2022, Vol. 49 ›› Issue (4): 167-175.doi: 10.19665/j.issn1001-2400.2022.04.019

• 电子科学与技术 & 其他 • 上一篇下一篇

抗电磁侧信道攻击随机预混淆逻辑单元设计

赵毅强¹(),曹宇文¹(),何家骥¹(),马浩诚¹(),刘燕江²(),叶茂¹()

1.天津大学微电子学院,天津 300072
2.中国人民解放军战略支援部队信息工程大学密码工程学院,河南郑州 450001

收稿日期:2021-04-21 出版日期:2022-08-20 发布日期:2022-08-15
通讯作者: 何家骥
作者简介:赵毅强(1964—),男,教授,博士,E-mail: yq_zhao@tju.edu.cn|曹宇文(1996—),男,天津大学硕士研究生,E-mail: yuwen_c@tju.edu.cn|马浩诚(1996—),男,天津大学博士研究生,E-mail: hc_ma@tju.edu.cn|刘燕江(1990—),男,博士,E-mail: liuyj_1013@126.com|叶茂(1987—),男,副教授,博士,Email: mao_ye@tju.edu.cn
基金资助:
国家自然科学基金重点基金(61832018);国家自然科学基金青年科学基金(62004112)

Design of random pre-obfuscation logic units against EM side-channel attack

ZHAO Yiqiang¹(),CAO Yuwen¹(),HE Jiaji¹(),Ma Haocheng¹(),LIU Yanjiang²(),YE Mao¹()

1. School of Microelectronics,Tianjin University,Tianjin 300072,China
2. School of Cryptographic Engineering,the PLA Strategic Support Force Information Engineering University,Zhengzhou 450001,China

Received:2021-04-21 Online:2022-08-20 Published:2022-08-15
Contact: Jiaji HE

摘要/Abstract

摘要：

针对现场可编程门阵列实现的密码算法所面临的电磁侧信道安全威胁问题,通过分析现场可编程门阵列的底层硬件架构,提出了一种基于随机预混淆逻辑单元的抗电磁侧信道攻击防护方法。提出的方法用查找表架构来实现随机预混淆逻辑单元,通过在待防护电路设计中靶向插入随机预混淆逻辑单元,并利用现场可编程门阵列中的查找表和超前进位链片上资源进行相关时序调控,以隐藏组合逻辑的运算起始状态。同时能够掩盖时序逻辑的状态翻转,从而减小电磁侧信道泄露信噪比,最终达到降低电磁辐射与密钥相关性的目的。以高级加密标准电路作为验证基准,基于现场可编程门阵列进行电路实现,采集电路加密明文所产生的电磁辐射,使用相关性电磁侧信道分析方法破解电路密钥。实验结果表明,在应用所提出的防护方法后,破解密钥所需的电磁曲线数目从94提高至100 000以上,电磁侧信道安全性提高了1 000倍以上,该防护方法引入的逻辑资源开销仅为1.1%,功耗开销仅为1.47%,且并未引入额外的性能开销。

关键词: 现场可编程门阵列, 硬件安全, 电磁分析攻击, 侧信道防护

Abstract:

Due to the programmable features,FPGAs have been prevalent in security applications using cryptographic algorithms.Recently,electromagnetic side-channel analysis attacks have become a major threat to these hardware implementations.On the basis of the hardware architecture of field programmable gate arrays,we propose an electromagnetic side-channel countermeasure based on random pre-obfuscation logic units.These logic units are implemented using the look-up table architecture and inserted with elaborated timing adjustments,on the basis of which the initial state of the combinatorial logic and the state transition of the sequential logic are hidden,so as to reduce the correlation between electromagnetic radiation and the key.After applying the countermeasure to the Advanced Encryption Standard circuit,experimental results show that the number of electromagnetic curves required to crack the key increases from 94 to more than 100 000.This means that the electromagnetic side-channel security is improved by 1 000 times at least.In terms of overhead,the resource and power increase only by 1.1% and 1.47% respectively,with no additional performance overhead introduced.

Key words: field programmable gate arrays, hardware security, electromagnetic analysis attack, side channel countermeasure

中图分类号:

TN918.4

赵毅强,曹宇文,何家骥,马浩诚,刘燕江,叶茂. 抗电磁侧信道攻击随机预混淆逻辑单元设计[J]. 西安电子科技大学学报, 2022, 49(4): 167-175.

ZHAO Yiqiang,CAO Yuwen,HE Jiaji,Ma Haocheng,LIU Yanjiang,YE Mao. Design of random pre-obfuscation logic units against EM side-channel attack[J]. Journal of Xidian University, 2022, 49(4): 167-175.

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参考文献 19

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I₂	I₃	O₁	RPOL的模式
0	0	I₁	缓冲
0	1	I₁	缓冲
1	0	~I₄	振荡
1	1	I₁	缓冲

	Slice开销	FF开销	LUT开销	总逻辑资源开销	功耗开销	最高运行频率
优化前AES	944个	2 390个	1 705个	4 095个	2.73 mW	79.8 MHz
优化后AES	1 072个	2 362个	1 778个	4 140个	2.77 mW	81.5 MHz
开销占比	+13.6%	-1.2%	+4.3%	+1.1%	+1.47%	+2.1%

文献	验证平台	EMA方式	MTD增加倍数	额外逻辑开销	性能开销	功耗开销
文献[5]	28 nm FPGA	CEMA	>25x
文献[6]	28 nm FPGA	CEMA	63x			+18%
文献[16]	32 nm CMOS	模板分析	150x	+20%	-70%
文中方法	45 nm FPGA	CEMA	>1 063x	+1.1%	无影响	+1.47%

抗电磁侧信道攻击随机预混淆逻辑单元设计

Design of random pre-obfuscation logic units against EM side-channel attack

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