关键词: 专用集成电路, IP, 逻辑设计, 控制设备, 存储设备, 可重用性, 多端口, 仲裁器

Abstract:

In order to improve the memory bandwidth for masters accessing external memory in the SoC system, a multi-port memory controller IP core based on the AHB bus is developed. Also, an arbitration strategy for the early arbitration and request waiting priority is proposed. A number of masters in this IP core are requested to access the external memory through a number of ports. The arbitration selects the highest-priority port in the early arbitration moment and sets the request waiting time for the other ports that are not allowed the access request . The early arbitration moment occurs before the completion for the current read/write operations. When the next early arbitration moment happens, the arbitration arbitrates these timeout ports in preference. The results of simulation and hardware verification indicate that the maximum memory bandwidth is about 532MB/s and that the maximum bus utilization rate is about 90％.

Key words: application specific integrated circuits, intellectual property, logic design, control equipment, data storage equipment, reusability, multiport;arbiter