一种R-C-R组合式12位逐次逼近A／D转换器

doi:10.3969/j.issn.1001-2400.2010.05.023

J4 ›› 2010, Vol. 37 ›› Issue (5): 904-910.doi: 10.3969/j.issn.1001-2400.2010.05.023

一种R-C-R组合式12位逐次逼近A／D转换器

佟星元¹;陈杉²;蔡乃琼¹;朱樟明¹;杨银堂¹

(1. 西安电子科技大学微电子技术研究所，陕西西安 710071；
2. 苏州秉亮科技有限公司，江苏苏州 215021)

收稿日期:2009-12-15 出版日期:2010-10-20 发布日期:2010-10-11
通讯作者: 佟星元
作者简介:佟星元(1984-)，男，西安电子科技大学博士研究生，E-mail: mayxt@126.com．
基金资助:
国家自然科学基金资助项目(60725415,60971066,60676009,60776034,60803038);国家863计划资助项目(2009AA01Z258,2009AA01Z260);国家重大科技专项资助项目(2009ZX01034-002-001-005)

12-bit SAR A／D converter with an R-C-R hybrid architecture

TONG Xing-yuan¹;CHEN Shan²;CAI Nai-qiong¹;ZHU Zhang-ming¹;YANG Yin-tang¹

(1. Research Inst. of Microelectronics, Xidian Univ., Xi'an 710071， China;
2. Aicestar Technology Suzhou Company, Suzhou 215021， China)

Received:2009-12-15 Online:2010-10-20 Published:2010-10-11
Contact: TONG Xing-yuan

摘要/Abstract

摘要：

采用一种R-C-R组合式逐次逼近A／D转换方法，基于UMC 90nm CMOS工艺设计了一种12位1兆赫兹采样频率的逐次逼近型A／D转换器．在电路设计上，通过复用两段式电阻梯结构，有效地降低了系统对电容阵列的匹配性要求．在版图设计方面，采用了特殊的电阻梯版图设计方法来减小连接电阻的失配影响，并采用金属叉指电容来提高工艺兼容性以减小工艺成本．在3.3V模拟电源电压和1.0V数字电源电压下，测得微分非线性为0.78最低有效位．当采样速率为1兆采样点每秒，输入信号频率为10kHz时，测得的有效位数为10.3，包括输出驱动在内，功耗不足10mW．整个转换器的有源面积小于0.31mm²，符合嵌入式片上系统的应用要求．

关键词: A／D转换器, 逐次逼近, 两段式电阻梯, 金属叉指电容, 低成本

Abstract:

This paper focuses on the research on the SAR (Successive-Approximation-Register) A／D converter. An R-C-R combination based SAR A／D conversion approach is discussed and a 12-bit 1MSamples/s SAR A／D converter is realized with this approach in the UMC 90nm CMOS process. In circuit design, the matching requirement for the capacitor array is alleviated by utilizing a reusable two-segment resistor string. In layout design, a special resistor layout design method is used to reduce impact on linearity from the mismatch of connection resistors. Metal finger capacitors are adopted to improve technology compatibility and reduce the cost. With a 3.3V analog supply and a 1.0V digital supply, the differential non-linearity of this converter is measured to be 0.78LSB (Least-Significant-Bit). At the sampling rate of 1MSamples/s and the input frequency of 10kHz, the ENOB (Effective-Number-of-Bits) is measured to be 10.3 and the power dissipation is measured to be less than 10mW including that of the output drivers. The active area of the converter is about 0.31mm². This converter can satisfy the embedded SoC (System-on-Chip) applications.

Key words: A／D converter, successive approximation register, two-segment resistor string, metal finger capacitor, low cost

佟星元;陈杉;蔡乃琼;朱樟明;杨银堂. 一种R-C-R组合式12位逐次逼近A／D转换器[J]. J4, 2010, 37(5): 904-910.

TONG Xing-yuan;CHEN Shan;CAI Nai-qiong;ZHU Zhang-ming;YANG Yin-tang. 12-bit SAR A／D converter with an R-C-R hybrid architecture[J]. J4, 2010, 37(5): 904-910.

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一种R-C-R组合式12位逐次逼近A／D转换器

12-bit SAR A／D converter with an R-C-R hybrid architecture

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