一种用于人脸检测SoC中的加速协处理器设计

doi:10.3969/j.issn.1001-2400.2011.03.013

J4 ›› 2011, Vol. 38 ›› Issue (3): 76-82.doi: 10.3969/j.issn.1001-2400.2011.03.013

一种用于人脸检测SoC中的加速协处理器设计

焦继业¹；穆荣²；郝跃¹

(1. 西安电子科技大学宽禁带半导体材料与器件教育部重点实验室，陕西西安 710071；
2. 西安科技大学网络中心，陕西西安 710054)

收稿日期:2010-08-30 出版日期:2011-06-20 发布日期:2011-07-14
通讯作者: 焦继业
作者简介:焦继业(1977-)，男，西安电子科技大学博士研究生，E-mail: jiaojy@gamil.com．
基金资助:
陕西省自然科学基金资助项目(2009JM8004)

Co-processor implementation for fast face detection in a system-on-chip

JIAO Jiye¹；MU Rong²；HAO Yue¹

(1. Ministry of Education Key Lab. of Wide Band-Gap Semiconductor Materials and Devices, Xidian Univ., Xi'an 710071， China|
2. Network Center, Xi'an Univ. of Science and Technology, Xi'an 710054， China)

Received:2010-08-30 Online:2011-06-20 Published:2011-07-14
Contact: JIAO Jiye

摘要/Abstract

摘要：

提出了一种改进的、适合硬件并行实现的Adaboost算法多层分类器协处理器架构．该协处理器由积分图数据快速读取模块、多层分类器Haar型特征值运算模块、DMA数据存取模块和协处理器接口模块组成，模块间采用流水线以及FIFO缓存实现数据并行处理，用于人脸检测SoC中加速人脸检测迭代过程．将该协处理器嵌入一个实际的人脸检测SoC中，只增加了SoC的少量面积，却明显提高了人脸检测的处理速度．人脸检测SoC在CYCLONE-Ⅱ EP2C70 FPGA上通过验证．实验结果显示，在系统工作频率为70MHz时，能以10帧每秒的处理速度检测彩色QVGA图像中的人脸．

关键词: 人脸检测, Adaboost算法, 多层分类器, 协处理器

Abstract:

An improved co-processor architecture suitable for hardware parallel implementation is proposed to perform the feature classification based on the Adaboost algorithm. The co-processor consists of image quick access module, module for calculating the Haar features, DMA data transfer module, and interface to the co-processor module. Modules use the pipeline and FIFO buffer to process data to accelerate the iterative process of face detection. The co-processor only increases a small area in face detection SoC, but significantly improves the speed of face detection. In addition, we implement the proposed SoC on a CYCLONE-Ⅱ EP2C70 FPGA to show that object detection can be achieved at 10 frames per second at the system operating frequency of 70MHz on color QVGA camera video.

Key words: face detection, Adaboost algorithm, features classifiers, co-processor

中图分类号:

TP391

焦继业；穆荣；郝跃. 一种用于人脸检测SoC中的加速协处理器设计[J]. J4, 2011, 38(3): 76-82.

JIAO Jiye；MU Rong；HAO Yue. Co-processor implementation for fast face detection in a system-on-chip[J]. J4, 2011, 38(3): 76-82.

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一种用于人脸检测SoC中的加速协处理器设计

Co-processor implementation for fast face detection in a system-on-chip

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