漏极接触孔到栅间距对GGNMOS保护器件的影响

doi:10.3969/j.issn.1001-2400.2014.04.005

J4 ›› 2014, Vol. 41 ›› Issue (4): 26-30.doi: 10.3969/j.issn.1001-2400.2014.04.005

漏极接触孔到栅间距对GGNMOS保护器件的影响

吴晓鹏;杨银堂;董刚;高海霞

(西安电子科技大学宽禁带半导体材料与器件教育部重点实验室，陕西西安 710071)

收稿日期:2013-03-26 出版日期:2014-08-20 发布日期:2014-09-25
通讯作者: 吴晓鹏
作者简介:吴晓鹏(1979-)，女，西安电子科技大学博士研究生，E-mail:xpwu@mail.xidian.edu.cn．
基金资助:
国家部委预研究基金资助项目(9140A23060111)；陕西省科技统筹创新工程计划资助项目(2011KTCQ01-19)；中央高校基本科研业务费专项资金资助项目(K5051325011)

Influence of drain contact to gate space on the characteristic of the GGNMOS protection device

WU Xiaopeng;YANG Yintang;DONG Gang;GAO Haixia

(Ministry of Education Key Lab. of Wide Band-Gap Semiconductor Materials and Devices, Xidian Univ., Xi'an 710071， China)

Received:2013-03-26 Online:2014-08-20 Published:2014-09-25
Contact: WU Xiaopeng

摘要/Abstract

摘要：

研究了不同漏极接触孔到栅间距对深亚微米单叉指栅接地N型金属氧化物半导体静电放电保护器件性能的影响，并分析了相关物理机制．基于中芯国际018μm互补金属氧化物半导体工艺进行流片，并进行传输线脉冲测试，得到了不同漏极接触孔到栅间距(DCGS)值的保护器件单位宽度失效电流水平的变化趋势．结合器件仿真，分析了保护器件的电、热分布情况．研究结果表明，DCGS值的增大，使电流密度峰值向远离沟道的方向移动，从而降低了尖端放电的风险．同时，当DCGS值增大到一定阈值时，由于漏区与衬底温度达到平衡，因此失效电流水平出现饱和趋势．

关键词: 漏极接触孔到栅间距, 静电放电, 栅接地N型金属氧化物半导体

Abstract:

Based on the test data, the influence of DCGS on the single finger GGNMOS ESD protection device is investigated. The changing tendency of the failure current level is given by the TLP test under various layout parameter conditions realized in the SMIC 018μm CMOS process. Electrical and thermal distribution is detailed based on the device simulation. The results show that the peak value of the current density is moved in the opposite direction to the channel, which lowers the risk of LDD discharge. Meanwhile, the failure current level shows the saturation tendency because of the heat balance of the drain and substrate region which appears when the DCGS is raised to the threshold value.

Key words: drain contact to gate space (DCGS), electrostatic discharge (ESD), gate grounded NMOS (GGNMOS)

中图分类号:

TN406

吴晓鹏;杨银堂;董刚;高海霞. 漏极接触孔到栅间距对GGNMOS保护器件的影响[J]. J4, 2014, 41(4): 26-30.

WU Xiaopeng;YANG Yintang;DONG Gang;GAO Haixia. Influence of drain contact to gate space on the characteristic of the GGNMOS protection device[J]. J4, 2014, 41(4): 26-30.

参考文献

［1］ Fukasaku K, Yamazaki T, Kanno M. Origin of I_t₂ Drop Depending on Process and Layout with Fully Silicided GGMOS［C］//Electrical Overstress／Electrostatic Discharge Symposium. Piscataway: IEEE, 2011: 1-6.
［2］ Iyer N M, Jiang H, Yap H K, et al. Engineering Fully Silicided Large MOSFET Driver for Maximum I_t₁ Performance［C］//Electrical Overstress／Electrostatic Discharge Symposium. Piscataway: IEEE, 2010: 1-6.
［3］ Iyer N M, Jiang H, Yap H K, et al. ESD Engineering Fully Silicided Large MOSFET Driver for Maximum I_t₁ Performance［J］. IEEE Transactions on Device and Materials Reliability, 2011, 11(4): 516-521.
［4］刘红侠, 刘青山. 018μm CMOS工艺下的新型ESD保护电路设计［J］. 西安电子科技大学学报, 2009, 36(5): 867-870.
Liu Hongxia, Liu Qingshan. Analysis and Design of Novel ESD Protection Circuit in 018μm CMOS Process ［J］. Journal of Xidian University, 2009, 36(5): 867-870.
［5］杜鸣, 郝跃. CMOS工艺中栅耦合ESD保护电路［J］. 西安电子科技大学学报, 2006, 33(4): 547-549.
Du Ming, Hao Yue. Design of the ESD Protection Circuit with the Gate-couple Technique in CMOS Technology［J］. Journal of Xidian University, 2006, 33(4): 547-549.
［6］ Chen T, Ker M. Analysis on the Dependence of Layout Parameters on ESD Robustness of CMOS Devices for Manufacturing in Deep-submicron CMOS Process［J］. IEEE Transactions on Semiconductor Manufacturing, 2003, 16(3): 486-500.
［7］ Amerasekera E A, Duvvury C, Anderson W, et al. ESD in Silicon Integrated Circuits［M］. New York: Wiley, 2002: 328.
［8］吴晓鹏, 杨银堂, 高海霞, 等. 基于深亚微米工艺的栅接地NMOS静电放电保护器件衬底电阻模型研究［J］. 物理学报, 2013, 62(4): 047203.
Wu Xiaopeng, Yang Yintang, Gao Haixia, et al. A Compact Model of Substrate Resistance for Deep Sub-micron Gate Grounded NMOS Electrostatic Discharge Protection Device ［J］. Acta Physica Sinica, 2013, 62(4): 047203.
［9］ Oh K, Duvvury C, Banerjee K, et al. Investigation of Gate to Contact Spacing Effect on ESD Robustness of Salicided Deep Submicron Single Finger NMOS Transistors［C］//Reliability Physics Symposium Proceedings. Piscataway: IEEE, 2002: 148-155.
［10］ Mohan N, Kumar A. Modeling ESD Protection［J］. IEEE Potentials, 2005, 24(1): 21-24.
［11］ Ker M, Chen T. Substrate-triggered Technique for On-chip ESD Protection Design in a 018μm Salicided CMOS Process［J］. IEEE Transactions on Electron Devices, 2003, 50(4): 1050-1057.
［12］ Zurich Integrated Systems Engineering Incorporated. ISE-TCAD Dessis Simulation User's Manual［M］. Zurich: Integrated Systems Engineering, 2005: 55-56.

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[5]	刘红侠;刘青山. 0.18μm CMOS工艺下的新型ESD保护电路设计[J]. J4, 2009, 36(5): 867-870+926.
[6]	朱志炜;郝跃;方建平;刘红侠. 静电放电应力下深亚微米栅接地NMOSFET源端热击穿机理 [J]. J4, 2006, 33(6): 911-916.
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漏极接触孔到栅间距对GGNMOS保护器件的影响

Influence of drain contact to gate space on the characteristic of the GGNMOS protection device

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