90nm CMOS工艺下3×VDD容限静电检测电路

doi:10.3969/j.issn.1001-2400.2015.01.009

J4 ›› 2015, Vol. 42 ›› Issue (1): 56-61+206.doi: 10.3969/j.issn.1001-2400.2015.01.009

90nm CMOS工艺下3×V_DD容限静电检测电路

杨兆年;刘红侠;朱嘉

(西安电子科技大学宽禁带半导体材料与器件教育部重点实验室，陕西西安 710071)

收稿日期:2013-10-19 出版日期:2015-02-20 发布日期:2015-04-14
通讯作者: 杨兆年
作者简介:杨兆年(1986-)，男，西安电子科技大学博士研究生，E-mail：e_yangzhaonian@sina.com．
基金资助:
国家自然科学基金资助项目(61376099, 11235008)；教育部博士点基金资助项目(20130203130002, 20110203110012)

3×V_DD-tolerant ESD detection circuit in a 90nm CMOS process

YANG Zhaonian;LIU Hongxia;ZHU Jia

(Ministry of Education Key Lab. of Wide Band-Gap Semiconductor Materials and Devices, Xidian Univ., Xi'an 710071, China)

Received:2013-10-19 Online:2015-02-20 Published:2015-04-14
Contact: YANG Zhaonian

摘要/Abstract

摘要：

提出一种90nm 1.2V CMOS工艺下只用低压器件的新型3×V_DD容限的静电检测电路．该电路利用纳米工艺MOSFET的栅极泄漏特性和反馈技术来控制触发晶体管并进而开启箝位器件(可控硅整流器)，同时采用多级叠加结构以承受高电压应力．在静电放电时，该电路能产生38mA的触发电流．在3×V_DD电压下工作时，每个器件都处于安全电压范围，在25℃时漏电流仅为52nA．仿真结果表明，该检测电路可成功用于3×V_DD容限的接口缓冲器．

关键词: 检测电路, 静电泄放, 反馈, 泄漏特性, 叠加晶体管

Abstract:

A new low leakage 3×V_DD-tolerant electrostatic discharge (ESD) detection circuit only using the low-voltage device is proposed in a 90nm 1.2V CMOS process. Gate leaky characteristics of the nanoscale MOSFET and the feedback technique are used to control the trigger MOSFET and turn on the clamp device silicon-controlled rectifier (SCR). The multi-stage stacked-transistors structure is used to sustain a high voltage stress. The proposed detection circuit can generate 38mA current to turn on the clamp device SCR under the ESD stress. Under normal 3×V_DD operating conditions, all the devices are free from over-stress voltage threat. The leakage current is 52nA under the 3×V_DD bias at 25℃. Simulation result shows that the circuit can be successfully used for the 3×V_DD-tolerant I/O buffer.

Key words: detection circuit, electrostatic discharge, feedback, leaky characteristic, stacked transistors

中图分类号:

TN495

杨兆年;刘红侠;朱嘉. 90nm CMOS工艺下3×V_DD容限静电检测电路[J]. J4, 2015, 42(1): 56-61+206.

YANG Zhaonian;LIU Hongxia;ZHU Jia. 3×V_DD-tolerant ESD detection circuit in a 90nm CMOS process[J]. J4, 2015, 42(1): 56-61+206.

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90nm CMOS工艺下3×V_DD容限静电检测电路

3×V_DD-tolerant ESD detection circuit in a 90nm CMOS process

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90nm CMOS工艺下3×VDD容限静电检测电路

3×VDD-tolerant ESD detection circuit in a 90nm CMOS process

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90nm CMOS工艺下3×V_DD容限静电检测电路

3×V_DD-tolerant ESD detection circuit in a 90nm CMOS process