关键词: 离散小波变换, 超大规模集成电路, 集成电路设计, 无乘法器, 无片外存储

Abstract:

Two-dimensional(2-D) Discrete Wavelet Transform(DWT) is a commonly used image processing method. Due to its large amount of computation, it is often implemented in the hardware circuit to meet the need of high throughput. The existing hardware architectures have a large storage requirement for the input data. Therefore, a hardware efficient 2-D DWT architecture using the line-based and dual-scan method without multipliers is proposed. The total ram requirement of the proposed architecture is reduced to 10N bytes, while the off-chip RAM is not required. Besides, a Critical Path Delay(CPD) of one full-adder delay is achieved by using Canonic Sign Digit(CSD) multipliers. The estimated hardware requirement shows that the proposed architecture involves at least a 4％ smaller number of transistors and 33％ less transistor count-delay-product(TDP) than the existing architectures.

Key words: discrete wavelet transforms, very large scale integration, integrated circuit design, multiplier-less, off-chip random access memory less