一种新型低存储二维离散小波变换架构

doi:10.3969/j.issn.1001-2400.2018.02.019

摘要/Abstract

摘要：

由于现有二维离散小波变换硬件结构通常存在输入图像存储空间较大和硬件资源消耗较高的问题，制约了系统的硬件效率提升．为此，调整了输入数据的时序，设计了一种基于提升算法的新型二维离散小波变换架构．采用了横向并行、数据错位的三输入扫描方法，降低了处理模块的硬件资源消耗，同时消除了片外存储的需求．对于一幅长宽为N×N的输入图像，系统的总存储需求缩减为9N字节．经过硬件分析，对比其他现有结构，本架构的硬件效率提升了8％以上．

关键词: 离散小波变换, 超大规模集成电路, 集成电路设计, 数据错位扫描, 无片外存储

Abstract:

Two-dimensional (2-D) Discrete Wavelet Transform (DWT) is a commonly used method in digital signal processing, image analysis and image compression. Due to its large amounts of computation, it is often implemented in a hardware circuit. In general, the hardware architectures have a large input RAM and large hardware resources, which restrict the improvement of system hardware efficiency. Therefore, a memory efficient 2-D DWT architecture based on the lifting scheme is proposed in this paper. The order of input data is adjusted, horizontal parallel scanning and data dislocation 3-input method are introduced in this work for reducing hardware resources and eliminating the off-chip RAM. For an image size of N×N, the total ram requirement of the proposed architecture is reduced to 9N bytes. The estimated hardware requirement shows that at least 8％ less transistor count-delay-product (TDP) can be saved compared with the existing architectures.

Key words: discrete wavelet transforms, very large scale integration, integrated circuit design, data dislocation method, off-chip random access memory less

高家明;梁煜;张为;刘艳艳. 一种新型低存储二维离散小波变换架构[J]. 西安电子科技大学学报, 2018, 45(2): 110-115.

GAO Jiaming;LIANG Yu;ZHANG Wei;LIU Yanyan. Memory efficient architecture for 2-D DWT[J]. Journal of Xidian University, 2018, 45(2): 110-115.

参考文献

［1］ ZHANG W, JIANG Z, GAO Z, et al. An Efficient VLSI Architecture for LIfting-based Discrete Wavelet Transform［J］. IEEE Transactions on Circuits and Systems Ⅱ: Express Briefs, 2012, 59(3): 158-162.
［2］ DARJI A, AGRAWAL S, OZA A, et al. Dual-scan Parallel Flipping Architecture for a Lifting-based 2-D Discrete Wavelet Transform［J］. IEEE Transactions on Circuits and Systems Ⅱ: Express Briefs, 2014, 61(6): 433-437.
［3］ YE L N, HOU Z. Memory Efficient Multilevel Discrete Wavelet Transform Schemes for JPEG2000［J］. IEEE Transactions on Circuits and Systems for Video Technology, 2015, 25(11): 1773-1785.
［4］ HU Y S, JONG C C. A Memory-efficient Scalable Architecture for Lifting-based Discrete Wavelet Transform［J］. IEEE Transactions on Circuits and Systems Ⅱ: Express Briefs, 2013, 60(8): 502-506.
［5］ MOHANTY B K, MEHER P K. Area-delay-power-efficient Architecture for Folded Two-dimensional Discrete Wavelet Transform by Multiple Lifting Computation［J］. IET Image Processing, 2014, 8(6): 345-353.
［6］ MOHANTY B K, MEHER P K, SRIKANTHAN T. Critical-path Optimization for Efficient Hardware Realization of Lifting and Flipping DWTs［C］//Proceedings of the 2015 IEEE International Symposium on Circuits and Systems. Piscataway: IEEE, 2015: 1186-1189.
［7］ TODKAR S, SHASTRY P V S. Flipping Based High Performance Pipelined VLSI Architecture for 2-D Discrete Wavelet Transform［C］//Proceedings of the 2015 International Conference on Applied and Theoretical Computing and Communication Technology. Piscataway: IEEE, 2015: 832-836.
［8］ DARJI A D, LIMAYE A. Memory Efficient VLSI Architecture for Lifting-based DWT［C］//Proceedings of the 2014 Midwest Symposium on Circuits and Systems. Piscataway: IEEE, 2014: 189-192.
［9］ HU Y, JONG C C. A Memory-efficient High-throughput Architecture for Lifting-based Multi-Level 2-D DWT［J］. IEEE Transactions on Signal Processing, 2013, 61(20): 4975-4987.
［10］ MOHANTY B K, MAHAJAN A, MEHER P K. Area- and Power-efficient Architecture for High-throughput Implementation of Lifting 2-D DWT［J］. IEEE Transactions on Circuits and Systems Ⅱ: Express Briefs, 2012, 59(7): 434-438.
［11］ HUANG C T, TSENG P C, CHEN L G. Flipping Structure: an Efficient VLSI Architecture for Lifting-based Discrete Wavelet Transform［J］. IEEE Transactions on Signal Processing, 2004, 52(4): 1080-1089.
［12］董明岩, 雷杰, 王柯俨, 等. 高效低存储DWT的VLSI结构设计［J］. 西安电子科技大学学报, 2016, 43(2): 35-40.
DONG Mingyan, LEI Jie, WANG Keyan, et al. Highly Efficient VLSI Architecture for DWT with Low-storage Implementation［J］. Journal of Xidian University, 2016, 43(2): 35-40.
［13］ HSIA C H, CHIANG J S, GUO J M. Memory-efficient Hardware Architecture of 2-D Dual-mode Lifting-based Discrete Wavelet Transform［J］. IEEE Transactions on Circuits and Systems for Video Technology, 2013, 23(4): 671-683.
［14］ WU C K, ZHANG W, JIA Q, et al. Hardware Efficient Multiplier-less Multi-level 2D DWT Architecture without off-chip RAM［J］. IET Image Processing, 2017, 11(6): 362-369.
［15］贾琦, 梁煜, 张为. 一种无片外存储的高性能二维DWT架构［J］. 西安电子科技大学学报, 2017, 44(4): 150-155.
JIA Qi, LIANG Yu, ZHANG Wei. Hardware Efficient 2-D DWT Architecture without off-chip RAM［J］. Journal of Xidian University, 2017, 44(4): 150-155.
［16］ MOHANTY B K, MEHER P K. Memory Efficient Modular VLSI Architecture for Highthroughput and Low-latency Implementation of Multilevel Lifting 2-D DWT［J］. IEEE Transactions on Signal Processing, 2011, 59(5): 2072-2084.

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