0.18μm CMOS工艺下的新型ESD保护电路设计

J4 ›› 2009, Vol. 36 ›› Issue (5): 867-870+926.

0.18μm CMOS工艺下的新型ESD保护电路设计

刘红侠;刘青山

(西安电子科技大学宽禁带半导体材料与器件教育部重点实验室，陕西西安 710071)

收稿日期:2008-06-23 出版日期:2009-10-20 发布日期:2009-11-30
通讯作者: 刘红侠
基金资助:
国家自然科学基金资助(60206006);教育部新世纪优秀人才计划资助(681231366);国家部委预研基金资助(51308040103);西安应用材料创新基金资助(XA-AM-200701)

Analysis and design of novel ESD protection circuit in 0.18μm CMOS process

LIU Hong-xia;LIU Qing-shan

(Ministry of Education Key Lab. of Wide Band-Gap Semiconductor Materials and Devices, Xidian Univ., Xi'an 710071， China)

Received:2008-06-23 Online:2009-10-20 Published:2009-11-30
Contact: LIU Hong-xia

摘要/Abstract

摘要：

为了有效地保护0.18μm CMOS工艺下箝位器件的栅极,设计了一款新型的电源和地之间的静电保护电路．该电路在检测电路部分加了一个NMOS反馈器件，同时在检测电路的下一级使用了动态传输结构.反馈器件能够提高电路中各器件工作状态的转换速度，使得保护电路能够及时关闭，避免箝位器件栅极电流保持过长时间，保护了箝位器件的栅极．此外，该电路采用0.18μm CMOS工艺下的普通器件，节省了电路的成本．

关键词: 静电放电, 保护电路, 反馈, 动态传输

Abstract:

Based on the 0.18μm CMOS process, a new type of power-rail ESD protection circuit for protecting the gate of the ESD clamp device is proposed. An NMOS feedback device is added in the detection circuit, and the dynamic transmission structure is applied. The working states are enhanced by the feedback structure, which can shutdown the protection circuit immediately, reduce the hold time of the current across the gate of the clamp device, and protect the gate. This circuit uses the normal devices for the 0.18μm CMOS process, thus saving the cost greatly. The effectiveness of this new protection circuit is verified by the research results.

Key words: electro-static discharge(ESD), protection circuits, feedback, dynamic transmission

中图分类号:

TN431.1

刘红侠;刘青山. 0.18μm CMOS工艺下的新型ESD保护电路设计[J]. J4, 2009, 36(5): 867-870+926.

LIU Hong-xia;LIU Qing-shan. Analysis and design of novel ESD protection circuit in 0.18μm CMOS process[J]. J4, 2009, 36(5): 867-870+926.

参考文献

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