一种面向片上网络的多时钟路由器设计

doi:10.3969/j.issn.1001-2400.2011.02.026

J4 ›› 2011, Vol. 38 ›› Issue (2): 146-150.doi: 10.3969/j.issn.1001-2400.2011.02.026

一种面向片上网络的多时钟路由器设计

刘毅^1,2;杨银堂^1,2;周东红¹

(1. 西安电子科技大学微电子学院，陕西西安 710071;
2. 西安电子科技大学宽禁带半导体材料与器件教育部重点实验室，陕西西安 710071)

收稿日期:2010-09-08 出版日期:2011-04-20 发布日期:2011-05-26
通讯作者: 刘毅
作者简介:刘毅(1971-)，男，副教授，E-mail: yiliu@mail.xidian.edu.cn．
基金资助:
国家杰出青年基金资助项目(60725415);国家自然科学基金资助项目(60676009,60776034);中央高校基本科研业务费专项资金资助项目(K50510250004)

Multi-clock router designed for the network-on-chip

LIU Yi^1,2;YANG Yintang^1,2;ZHOU Donghong¹

(1. School of Microelectronic, Xidian Univ., Xi'an 710071， China;
2. Ministry of Education Key Lab. of Wide Band-Gap Semiconductor Materials and Devices, Xidian Univ., Xi'an 710071， China)

Received:2010-09-08 Online:2011-04-20 Published:2011-05-26
Contact: LIU Yi

摘要/Abstract

摘要：

路由器是实现片上网络(Network-on-Chip, NoC)的核心组件．针对NoC不同时钟域间通信问题，以双时钟异步FIFO替代一般路由器中的跨时钟域接口电路，提出了一种适用于二维网格拓扑结构NoC的多时钟路由器结构．采用Verilog语言完成相关设计工作，FPGA综合结果表明该路由器占用资源少，工作频率可达475.29MHz，有效提高了数据传输速率．基于SMIC 0.13μm CMOS工艺，对不同深度FIFO的多时钟路由器综合结果进行比较，进一步分析了缓存大小对路由器性能和成本的影响．

关键词: 片上网络, 路由器, 多时钟

Abstract:

The router is a core element of the NoCs(Network-on-Chips). Aiming at NoC communication issues among different clock domains, the paper proposes a multi-clock router microarchitecture, which applies to 2D mesh topology NoC and uses dual-clock asynchronous FIFOs(First In First Out) instead of cross-clock domain interface circuits in usual routers. Designed by the Verilog HDL, the router's integrated results on FPGA show that it uses fewer resources and operates at a high frequency of up to 475.29MHz, effectively increasing the data transmission rate. Based on SMIC 0.13μm CMOS technology, by comparing the integrated results of routers with different FIFO depth values, impacts of the buffer size on the router's performance and cost are analyzed further.

Key words: network-on-chip, router, multi-clock

中图分类号:

刘毅;杨银堂;周东红. 一种面向片上网络的多时钟路由器设计[J]. J4, 2011, 38(2): 146-150.

LIU Yi;YANG Yintang;ZHOU Donghong. Multi-clock router designed for the network-on-chip[J]. J4, 2011, 38(2): 146-150.

参考文献

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一种面向片上网络的多时钟路由器设计

Multi-clock router designed for the network-on-chip

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