高效低存储DWT的VLSI结构设计

doi:10.3969/j.issn.1001-2400.2016.02.007

西安电子科技大学学报 ›› 2016, Vol. 43 ›› Issue (2): 35-40.doi: 10.3969/j.issn.1001-2400.2016.02.007

高效低存储DWT的VLSI结构设计

董明岩;雷杰;王柯俨;李云松

(西安电子科技大学综合业务网理论及关键技术国家重点实验室，陕西西安 710071)

收稿日期:2014-11-11 出版日期:2016-04-20 发布日期:2016-05-27
通讯作者: 雷杰
作者简介:董明岩(1990-)，男，西安电子科技大学硕士研究生，E-mail：962383739@qq.com．
基金资助:
国家优秀青年基金资助项目(61222101)；国家自然科学基金资助项目(61301287, 61301291)；高等学校学科创新引智计划资助项目(B08038)；中央高校基本科研业务费专项资金资助项目(K5051301043)

Highly efficient VLSI architecture for DWT with low-storage implementation

DONG Mingyan;LEI Jie;WANG Keyan;LI Yunsong

(State Key Lab. of Integrated Service Networks, Xidian Univ., Xi'an 710071, China)

Received:2014-11-11 Online:2016-04-20 Published:2016-05-27
Contact: LEI Jie

摘要/Abstract

摘要：

随着航天器载荷相机图像分辨率的日益提高，迫切需要解决海量图像数据的在轨高速编码处理问题，空间数据系统咨询委员会提出了一种面向空间应用的图像编码标准．为了保证较高的图像编码性能，该标准采用小波的变换方法．小波变换的多级变换形式比较耗时，且需要较大的存储开销．针对这一问题，提出了一种高效低存储离散小波变换的超大规模集成电路结构．通过改进传统的小波提升结构，将二三级变换和缓存结构进行复用，在不降低数据处理速度的情况下，节省了逻辑资源开销；使用少量片上存储资源存储部分小波系数，按特定顺序连续地输出给后级熵编码器进行处理，避免了使用片外存储．所提出的超大规模集成电路结构在Xilinx型号为XC4VSX55的现场可编程门阵列得到了硬件实现，具有95.91MPixels/s的数据处理性能．

关键词: 图像处理, 离散小波变换, 现场可编程门阵列, 超大规模集成电路

Abstract:

With the gradual increase in image resolution of the spacecraft camera, it is highly required to figure out the problem how to process a huge amount of image data on board at a high speed. As a solution, the CCSDS proposes a space-oriented image-coding standard. For the sake of high image-coding performance, it adopts wavelet transformation as a method of image data transformation. However, wavelet transformation contains multi-level data processing, which causes more computational time consumption and more memory utilization. In order to solve this problem, we propose a highly efficient VLSI architecture for DWT with low-storage. By revising the traditional lifting structure and employing time-multiplex data processing strategy to perform the second and third level of wavelet transformation by the same logic module, the usage of logic resource is reduced with no sacrifice on speed.Using a small amount of on-chip memory instead of off-chip memory to save certain parts of DWT coefficients and sending the coefficients in a specific sequence to entropy coder timely, the off-chip memory for storage of DWT coefficients is no longer required. The proposed VLSI architecture of DWT is already implemented on the Xilinx FPGA XC4VSX55, which can achieve a high performance, in terms of data throughput, reaching 95.91MPixels/s.

Key words: image processing, discrete wavelet transform(DWT), field programmable gate array(FPGA), very large scale integration(VLSI)

董明岩;雷杰;王柯俨;李云松. 高效低存储DWT的VLSI结构设计[J]. 西安电子科技大学学报, 2016, 43(2): 35-40.

DONG Mingyan;LEI Jie;WANG Keyan;LI Yunsong. Highly efficient VLSI architecture for DWT with low-storage implementation[J]. Journal of Xidian University, 2016, 43(2): 35-40.

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高效低存储DWT的VLSI结构设计

Highly efficient VLSI architecture for DWT with low-storage implementation

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