西安电子科技大学学报

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规则LDPC码在GPU上的加速译码

任计林;车书玲;郑征   

  1. (西安电子科技大学 综合业务网理论及关键技术国家重点实验室,陕西 西安 710071)
  • 收稿日期:2016-07-20 出版日期:2017-06-20 发布日期:2017-07-17
  • 作者简介:任计林(1990-),男,西安电子科技大学硕士研究生,E-mail: jlren@stu.xidian.edu.cn
  • 基金资助:

    国家自然科学基金资助项目(61101148);中央高校基本科研业务费专项资金资助项目(K5051301008)

Decoding of regular LDPC codes accelerated by the GPU

REN Jilin;CHE Shuling;ZHENG Zheng   

  1. (State Key Lab. of Integrated Service Networks, Xidian Univ., Xi'an 710071, China)
  • Received:2016-07-20 Online:2017-06-20 Published:2017-07-17

摘要:

针对图形处理器高速并行的特点和规则低密度奇偶校验码译码过程中的可并行部分,提出了使用图形处理器来加速规则低密度奇偶校验码译码的方法.该方法在图形处理器上采用以节点的边并行代替节点并行进行译码,提高了线程利用率; 同时,在译码过程中采用图形处理器高速的片上内存——共享内存和寄存器来存储数据,使数据存储减少对全局内存的依赖,缩短数据访问时间.仿真结果显示,使用边并行和片上内存,译码速度约是图形处理器不使用文中优化方法的低密度奇偶校验码译码程序的5.32~10.41倍.

关键词: 低密度奇偶校验码, 图形处理器, 统一计算设备架构, 并行计算, 共享内存, 寄存器

Abstract:

To take advantage of the high speed parallel feature of the GPU and the parallel section in the regular LDPC codes decoding process, a method is proposed by which the GPU is used to accelerate decoding of regular LDPC codes. In this method, edges of nodes are used in parallel decoding instead of nodes themselves to improve the utilization of threads. At the same time, the use of the high-speed on-chip GPU memory-shared memory and registers to store data makes data reduce dependence on global memory and shorten access time. Simulation results show that, by using parallel computing on edges and the on-chip memory, the decoding speed can be 5.32 ~ 10.41 times relative to the LDPC codes decoding program that does not use the optimization method of this paper based on the GPU.

Key words: low density parity-check(LDPC) codes, graphic processing unit(GPU), compute unified device architecture(CUDA), parallel computing, shared memory, registers

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