高速任意波形发生器数据通路的设计

doi:10.19665/j.issn1001-2400.2019.03.026

西安电子科技大学学报 ›› 2019, Vol. 46 ›› Issue (3): 173-179.doi: 10.19665/j.issn1001-2400.2019.03.026

高速任意波形发生器数据通路的设计

薛德宽^1,^2,³,李国扬¹,潘雪¹,范薇¹,李学春¹,朱健强¹

^1. 中国科学院上海光学精密机械研究所高功率激光物理联合实验室,上海 201800
^2. 中国科学院大学材料与光电研究中心,北京 100049
^3. 上海科技大学物质科学与技术学院,上海 200120

收稿日期:2019-03-04 出版日期:2019-06-20 发布日期:2019-06-19
作者简介:薛德宽(1994-),男,中国科学院上海光学精密机械研究所硕士研究生,E-mail: xuedk@siom.ac.cn.
基金资助:
国家自然科学基金(11604350)

Design of the data path of the high speed arbitrary waveform generator

XUE Dekuan^1,^2,³,LI Guoyang¹,PAN Xue¹,FAN Wei¹,LI Xuechun¹,ZHU Jianqiang¹

^1. National Laboratory on High Power Laser and Physics, Shanghai Institute of Optics and Fine Mechanics, Chinese Academy of Sciences, Shanghai 201800, China
^2. Center of Materials Science and Optoelectronics Engineering,University of the Chinese Academy of Sciences, Beijing 100049, China
^3. School of Physical Science and Technology, ShanghaiTech University, Shanghai 200120, China

Received:2019-03-04 Online:2019-06-20 Published:2019-06-19

摘要/Abstract

摘要：

针对任意波形发生器提升输出带宽和存储深度较难的问题,提出一种基于现场可编程门阵列器件的任意波形发生器数据通路设计方案。该方案利用多片同步动态随机存储器同步输出和并串转换技术提升数据通路的输出带宽和存储深度,基于Vivado平台实现波形数据的写入、读取、并串转换、成帧、8bit/10bit编码和串行化的功能,经过处理的波形数据通过现场可编程逻辑阵列的收发器以数据转换器串行传输协议输出。仿真结果表明,输出波形与写入波形存储器的波形数据经过上述数字信号处理之后的结果完全相同,验证了数据通路的正确性。实验结果表明,该数据通路实现了12 GHz的采样率、16 bit的垂直分辨率、4 Gsa的波形存储深度。该任意波形发生器数据通路设计是有效的和可靠的。

关键词: 波形生成, 现场可编程逻辑阵列, 并串转换, 串行传输

Abstract:

It is difficult to increase the output bandwidth and memory depth of an arbitrary waveform generator. A scheme for the data path of the high speed arbitrary waveform generator based on the Field Programmable Gate Array (FPGA) has been developed. In this scheme, the multi-chip synchronous dynamic random access memory synchronous output and parallel-to-serial conversion technology are used to improve the output bandwidth and memory depth of the data path. The data path implements data writing, reading, parallel-to-serial conversion, framing, 8bit/10bit encoding, and serialization based on the Vivado platform. The processed waveform data is serially outputted through FPGA's transceiver according to the JESD204B transmission protocol. Simulation results show that the output waveform data is exactly the same as the processed waveform data, which verifies the correctness of the data path. Experimental results show that the data path achieves a 12 GHz sampling rate, a 16 bit vertical resolution, and a 4 Gsa waveform memory. The data path of the arbitrary waveform generator is effective and reliable.

Key words: waveform generation, field programmable gate array, parallel-to-serial conversion, serial transmission

中图分类号:

TN97

薛德宽,李国扬,潘雪,范薇,李学春,朱健强. 高速任意波形发生器数据通路的设计[J]. 西安电子科技大学学报, 2019, 46(3): 173-179.

XUE Dekuan,LI Guoyang,PAN Xue,FAN Wei,LI Xuechun,ZHU Jianqiang. Design of the data path of the high speed arbitrary waveform generator[J]. Journal of Xidian University, 2019, 46(3): 173-179.

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参考文献 19

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技术方案	专用集成电路	低压差分信号	JESD204B
优点	速度高	方案简单	布线容易、成本低
缺点	成本高、周期长	速度低、布线复杂	数据通路设计难度高

目标时刻	合作态势推理概率
目标时刻	DBN算法	文中算法
t₁	0.623 4	0.623 4
t₂	0.563 3	0.604 4
t₄	0.580 8	0.622 2

高速任意波形发生器数据通路的设计

Design of the data path of the high speed arbitrary waveform generator

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