高性能EBCOT编码加速算法及其实现结构

doi:10.3969/j.issn.1001-2400.2010.04.002

Abstract

Abstract:

We propose an efficient coding algorithm and architecture composed of the bit plane-parallel and pass-parallel coder with efficient zero coefficients detection for EBCOT entropy encoder used in JPEG2000.After the detailed analysis of wavelet coefficients' precision and distribution in JPEG2000, there are three main modes of zero coefficients in the wavelet domain, i.e., zero column, zero stripe and zero code block. And we also discover that the coding information on each bit plane and the corresponding passes can be obtained simultaneously in the hardware structure. Therefore, bit plane-parallel and pass-parallel coding with zero detection (BPPP-ZD) is proposed, and its VLSI architecture is shown in detail. Analysis and the corresponding software/hardware experimental results show that the proposed architecture reduces the processing time greatly compared with other architechures, and a prototype chip is synthesized which can process 1024×1024 gray level images with 79 frames per second at the working frequency of 79.466MHz.

Key words: image compression, JPEG2000, embedded block coding with optimized truncation, zero detection

LIU Kai;LI Yun-song;GUO Jie. High performance EBCOT algorithm and VLSI architecture[J].J4, 2010, 37(4): 587-593.

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High performance EBCOT algorithm and VLSI architecture

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