［1］ Huang S, Levy B C. Blind Calibration of Timing Offsets for Four-Channel Time-Interleaved ADCs［J］. IEEE Trans on Circuits and Systems-I: Regular Papers, 2007, 54(4): 863-876.
［2］ McNeill J A, Coln M C W, Richard Brown D, et al. Digital Background-Calibration Algorithm for ‘Split ADC’ Architecture［J］. IEEE Trans on Circuits and Systems-I: Regular Papers, 2009, 56(2): 294-306.
［3］ Oshima T, Takahashi T, Yamawaki T. LMS Calibration of Sampling Timing for Time-interleaved A/D Converters［J］. Electronics Letters, 2009, 45(12): 615-617.
［4］ Dyer K C, Fu D, Lewis S H, et al. An Analog Background Calibration Technique for Time-Interleaved Analog-to-Digital Converters［J］. IEEE Journal of Solid-State Circuits, 1998, 33(12): 1912-1919.
［5］ Johansson H. Reconstraction of Nonuniformly Sampled Bandlimited Signals by Means of Digital Fractional Delay Filters［J］. IEEE Trans on Signal Processing, 2002, 50(11): 2757-2767.
［6］ Farrow C W. A Continuously Variable Digital Delay Element［C］//IEEE International Symposium on Circuits and Systems (ISCAS'88). Espoo: IEEE, 1988: 2641-2645.
［7］ Jenq Y C. Digital Spectra of Nonuniformly Sampled Signals: Fundamental and High-Speed Waveform Digitizers［J］. IEEE Trans on Inst and Meas, 1988, 37(2): 245-251.
［8］ Upadhyay D, Chaudhary V. Design of Variable Fractional Delay Filter Using DFT Interpolation［C］//IEEE International Conference on Advances in Recent Technologies in Communication and Computing. Kottayam: IEEE, 2009: 691-693.
［9］ Walczak K. Fractional Delay FIR filters Design with Enhanced Differential Evolution［J］. International Journal of Mathematical, Physical and Engineering Sciences, 2008, 65(43): 346-350.