针对乘法器内部加法运算次数的优化算法

doi:10.3969/j.issn.1001-2400.2013.03.015

J4 ›› 2013, Vol. 40 ›› Issue (3): 102-108.doi: 10.3969/j.issn.1001-2400.2013.03.015

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Optimization methodology for the number of additions in multiplier

YUAN Bo;LIU Hongxia

(Ministry of Education Key Lab. of Wide Band-Gap Semiconductor Materials and Devices, Xidian Univ., Xi'an 710071， China)

Received:2012-01-10 Online:2013-06-20 Published:2013-07-29
Contact: YUAN Bo E-mail:vias_yuan@tom.com

Abstract

Abstract:

This paper presents a low-power design methodology for the multiplier, whose optimization specification is the number of operations of the adders inside synthesized multiplier. The implementation technique resolves the problem of the optimization logic being introduced into the optimized system, which exists in present low power design. It can reduce system power and area significantly without an additional logic, a declined system working efficiency and a declined calculation accuracy. After a radio-frequency circuit is optimized, FPGA test results show that logic utilization is reduced by 32.1％, total registers number is reduced by 33.1％, and total block memory bits utilization is reduced by 35.4％. The methodology has good performance in optimizing the system including large-scale multipliers, such as DSP, digital filter, etc.

Key words: coefficient of multiplier, number of addition, optimization logic, power analysis

CLC Number:

TN702

YUAN Bo;LIU Hongxia. Optimization methodology for the number of additions in multiplier[J].J4, 2013, 40(3): 102-108.

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Optimization methodology for the number of additions in multiplier

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