近阈值非预充静态随机存储器

doi:10.3969/j.issn.1001-2400.2018.01.019

Abstract

Abstract:

In order to save the power consumed by the static random access memory when it deals with voice or video data, a novel memory cell is proposed which eliminates the precharge mechanism in the read operation, thus suppressing the invalid power compared with the conventional 6T and 8T cell. Furthermore, multiple threshold technology is employed in the cell, which not only guarantees the read static noise margin, but also enhances read ability. In addition, a Schmitt trigger based inverter is also applied in the cell array and hence it improves the read speed. Two memories including the proposed one and the conventional one are fabricated in 130nm process, respectively. Test results indicate that the proposed memory is excellent in reducing power consumption compared with the conventional 8T memory, and hence it becomes a suitable choice for the low power chips.

Key words: static random access memory, non-precharged, voice and video, low power

CAI Jiangzheng;HEI Yong;YUAN Jia;CHEN Liming. Near-threshold non-precharged SRAM[J].Journal of Xidian University, 2018, 45(1): 106-111.

References

［1］ CAI J Z, ZHANGA S M, YUAN J, et al. 320mV, 6kb Subthreshold 10T SRAM Employing Voltage Lowering Techniques［J］. Journal of Semiconductors, 2015, 36 (6): 065007.
［2］ DO A T, LEE Z C, WANG B, et al. 0.2V 8T SRAM with PVT-aware Bitline Sensing and Column-based Data Randomization［J］. IEEE Journal of Solid-State Circuits, 2016, 51(6): 1487-1498.
［3］ KIM T H, LIU J, KIM C H, et al. A Voltage Scalable 0.26V, 64kb 8T SRAM with V_min Lowering Techniques and Deep Sleep Mode［J］. IEEE Journal of Solide-State Circuit, 2009, 44(6):1785-1795.
［4］ LU C Y, CHUANG C T, JOU S J, et al. A 0.325V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-assist［J］. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2015, 23(5): 958-962.
［5］ ATIAS L, TEMAN A, GITERMAN R, et al. A Low-voltage Radiation-hardened 13T SRAM Bitcell for Ultralow Power Space Applications［J］. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016, 24(8):2622-2633.
［6］ WEN L, CHENG X, ZHOU K, et al. Bit-interleaving-enabled 8T SRAM with Shared Data-aware Write and Reference-based Sense Amplifier［J］. IEEE Transactions on Circuits and Systems Ⅱ: Express Briefs, 2016, 63(7): 643-647.
［7］ WANG B, NGUYEN T Q, DO A T, et al. Design of an Ultra-low Voltage 9T SRAM with Equalized Bitline Leakage and CAM-assisted Energy Efficiency Improvement［J］. IEEE Transactions on Circuits and Systems Ⅰ: Regular Papers, 2015, 62 (2):441-448.
［8］ CHANG I J, MOHAPATRA D, ROY K. A Priority-based 6T/8T Hybrid SRAM Architecture for Aggressive Voltage Scaling in Video Applications［J］. IEEE Transactions on Circuits and Systems for Video Technology, 2011, 21(2): 101-112.
［9］ DO A T, ZEINOLABEDIN S M A, KIM T T. A 0.3pJ/Access 8T Data-aware SRAM Utilizing Column-based Data Encoding for Ultra-low Power Applications［C］//Proceedings of the 2016 IEEE Asian Solid-State Circuits Conference. Piscataway: IEEE, 2017:173-176.
［10］ NOGUCHI H, IGUCHI Y, FUJIWARA H, et al. A 10T Non-precharge Two-port SRAM for 74％ Power Reduction in Video Processing［C］//Proceedings of the IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures. Piscataway: IEEE, 2007:107-112.
［11］ FUJIWARA H, NII K, NOGUCHI H, et al. Novel Video Memory Reduces 45％ of Bitline Power Using Majority Logic and Data-bit Reordering［J］. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2008, 16(6): 620-627.
［12］ CHIEN Y C CHIANG I H, WANG J S. Sub-threshold SRAM Bit Cell pnn for V_DDmin and Power Reduction［J］. Electronics Letters, 2014, 50(20): 1427-1429.

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Near-threshold non-precharged SRAM

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