一种高性能快速傅里叶变换的硬件设计

doi:10.3969/j.issn.1001-2400.2018.03.012

Abstract

Abstract:

This paper presents a hardware efficient Radix-2² Fast Fourier Transform (FFT) based on a single path delay feedback (SDF) architecture. The complex multipliers in previous architectures generally have some problems, such as a long critical path and hardware inefficiency. Because of the constant multiplicator in rotation factor multiplication, the constant multiplier is used to replace the traditional complex multiplier. Besides, a new method —“coefficient enlargement” is proposed to design the constant multiplier. By enlarging the coefficient of the rotation factor, the number of adders required for the corresponding constant multiplier is reduced to the minimum. This method reduces the consumption of hardware resources, shortens the critical path and improves the hardware efficiency. The 16-point FFT's maximum clock frequency can be up to 710MHz, and the area is about 0.12mm² under the 0.18μm ASIC technology. Compared to other architectures, the proposed architecture involves about 8％ less slice count and throughput per slice is doubled in the Xilinx Virtex-4 FPGAs and it involves about 44％ less LUT count and throughput per LUT is doubled in the Xilinx Virtex-5 FPGAs.

Key words: fast Fourier transform, single delay feedback, constant multiplier, coefficient enlargement

SHEN Yaopo;LIANG Yu;ZHANG Wei. Hardware efficient fast Fourier transform architecture[J].Journal of Xidian University, 2018, 45(3): 63-67+96.

References

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Hardware efficient fast Fourier transform architecture

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