传输触发架构的可编程神经网络处理器设计

doi:10.3969/j.issn.1001-2400.2018.04.017

Abstract

Abstract:

The convolutional neural networks have the problems of structure diversity and large amounts of data exchange and computation. A transport triggered architecture based convolutional neural network processor is presented in this paper. The data transport network is constructed with multi-channel direct memory access channels, the multi-port memory and the specialized pooling data path, which solves the inefficient data exchange problem. Experimental results show that, although the proposed architecture is 11% slower than the streamline structure, it can adapt to a variety of convolutional neural networks and save 46.5% multipliers. Compared with the schemes presented in other papers except pipeline implementation, our design improves the data throughput rate by 40% at least. Besides, this system has advantages of parallel efficiency, programmable flexibility, online architecture reconfiguration, high processing speed, etc.

Key words: deep learning, convolutional neural networks, parallel computing, field programmable gate array

ZHAO Boran;ZHANG Li;SHI Guangming;HUANG Rong;XU Xinran. Design of the programmable neural network processor based on the transport triggered architecture[J].Journal of Xidian University, 2018, 45(4): 92-98.

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Design of the programmable neural network processor based on the transport triggered architecture

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