0.18μm CMOS工艺下的新型ESD保护电路设计

Abstract

Abstract:

Based on the 0.18μm CMOS process, a new type of power-rail ESD protection circuit for protecting the gate of the ESD clamp device is proposed. An NMOS feedback device is added in the detection circuit, and the dynamic transmission structure is applied. The working states are enhanced by the feedback structure, which can shutdown the protection circuit immediately, reduce the hold time of the current across the gate of the clamp device, and protect the gate. This circuit uses the normal devices for the 0.18μm CMOS process, thus saving the cost greatly. The effectiveness of this new protection circuit is verified by the research results.

Key words: electro-static discharge(ESD), protection circuits, feedback, dynamic transmission

CLC Number:

TN431.1

LIU Hong-xia;LIU Qing-shan. Analysis and design of novel ESD protection circuit in 0.18μm CMOS process[J].J4, 2009, 36(5): 867-870+926.

References

［1］Ker M D. Whole-chip ESD Protection Design with Efficient VDD-to-VSS ESD Clamp Circuits for Submicron CMOS VLSI ［J］. IEEE Trans on Electronic Devices, 1999, 46(1): 173-183.
［2］Andrea C, Simone G, Augusto T, et al. Electrostatic Discharge Effects in Ultrathin Gate Oxide MOSFETs［J］. IEEE Trans on Devices and Materials Reliability, 2006, 6(1): 87-94.
［3］Smith J C, Boselli G. A MOSFET Power supply clamp with feedback enhanced triggering for ESD protection in advanced CMOS technologies ［J］. Microelectronics Reliability, 2005, 45(2): 201-202.
［4］Ker M D, Chen J H. Self-Substrate-Triggered Technique to Enhance Turn-On Uniformity of multi-Finger ESD Protection Devices ［J］. IEEE Solid-State Circuit, 2006, 41(11):2601-2609.
［5］Ker M D, Lin K H. The Impact of Low-holding-voltage Issue in High-voltage CMOS Technology and Design of Latchup-free Power-rail ESD Clamp Circuit for LCD Driver IC ［J］. IEEE Solid-State Circuit, 2005, 40(8):1751-1759.
［6］杜鸣, 郝跃. CMOS工艺下栅耦合ESD保护电路［J］. 西安电子科技大学学报, 2006, 33(4): 547-549.
Du Ming, Hao Yue. Design of the ESD Protection Circuit with the Gate-couple Technique in CMOS Technology ［J］. Journal of Xidian University, 2006, 33(4): 547-549.
［7］Chou H M, Lee J W, Li P Y. A Floating Gate Design for ESD Protection Circuits［J］. The VLSI Journal, 2007, 40(2): 161-166.
［8］Feng Haiqiang, Chen Guang, Zhan Rouying, et al. A Mixed-mode ESD Protection Circuits Simulation-design Methodology ［J］. IEEE Solid-State Circuit, 2003, 38(6): 995-1006.
［9］Ker M D, Chang W J. ESD Protection Design with On-chip ESD Bus and High-voltage-tolerant ESD Clamp Circuit for Mixed-voltage I/O Buffers ［J］. IEEE Solid-State Circuit, 2008, 55(6): 1409-1416.

[1]	GU Zhaojun,CHEN Hui,WANG Jialiang,GAO Bing. Target tracking control algorithm for small size quad-rotor helicopter [J]. Journal of Xidian University, 2021, 48(5): 117-127.
[2]	YU Lihong,ZHAO Jiaxiang. Design of sparse MIMO equalizers using least angle regression [J]. Journal of Xidian University, 2019, 46(1): 73-78.
[3]	CHEN Diping;DONG Gang. ESD power-rail clamp circuit with a 5V power in the 3.3V CMOS process [J]. Journal of Xidian University, 2018, 45(5): 96-101.
[4]	WU Yue;LV Hongliang;ZHANG Yuming;ZHANG Yimen. Design and implementation of a low-phase-noise GaAs HBT VCO [J]. Journal of Xidian University, 2018, 45(3): 30-34.
[5]	SHEN Yaopo;LIANG Yu;ZHANG Wei. Hardware efficient fast Fourier transform architecture [J]. Journal of Xidian University, 2018, 45(3): 63-67+96.
[6]	XIE Linlin;WANG Yang;QIAO Shushan;HEI Yong. Feedback tuning algorithm for fast-locking all-digital phase-locked loops [J]. Journal of Xidian University, 2018, 45(3): 91-96.
[7]	HOU Xiaojian;XU Hua;ZENG Leya. Variable step size multi-antenna diversity equalization algorithm using error feedback [J]. Journal of Xidian University, 2017, 44(5): 158-164.
[8]	ZHANG Tao;LI Kangkang;JIAO Haiquan. Low false alarm probability howling detection method [J]. Journal of Xidian University, 2017, 44(4): 100-105.
[9]	YANG Zhaonian;LIU Hongxia;ZHU Jia;FEI Chenxi. Voltage triggered ESD detection circuits in a 90nm CMOS process [J]. J4, 2015, 42(3): 54-60.
[10]	TANG Chengkai;LIAN Baowang;ZHANG Lingling. Dual loop Volterra filter predistortion in satellite communication [J]. J4, 2015, 42(3): 109-114.
[11]	YANG Zhaonian;LIU Hongxia;ZHU Jia. 3×V_DD-tolerant ESD detection circuit in a 90nm CMOS process [J]. J4, 2015, 42(1): 56-61+206.
[12]	SUN Jinhua;HAN Huimei;ZHU Jili. Reduced state demodulator for the SOQPSK-TG signal [J]. J4, 2014, 41(5): 1-6+12.
[13]	TIAN Xinji;LU Jing. New space-time coded transmission scheme for the X channel [J]. J4, 2014, 41(4): 116-122.
[14]	GUI Xin;KANG Guixia;ZHANG Ping. Adaptive bit partition algorithm in cooperative distributed antenna systems [J]. J4, 2013, 40(4): 149-154.
[15]	ZHAO Yongbin;HU Yupu;JIA Yanyan. New design of LFSR based stream ciphers to resist power attack [J]. J4, 2013, 40(3): 172-179+200.

Analysis and design of novel ESD protection circuit in 0.18μm CMOS process

PDF (PC)

Like

Knowledge

Abstract

Cite this article

share this article

References

Related Articles 15

Metrics

Comments

Recommended 0