高效低存储DWT的VLSI结构设计

doi:10.3969/j.issn.1001-2400.2016.02.007

Abstract

Abstract:

With the gradual increase in image resolution of the spacecraft camera, it is highly required to figure out the problem how to process a huge amount of image data on board at a high speed. As a solution, the CCSDS proposes a space-oriented image-coding standard. For the sake of high image-coding performance, it adopts wavelet transformation as a method of image data transformation. However, wavelet transformation contains multi-level data processing, which causes more computational time consumption and more memory utilization. In order to solve this problem, we propose a highly efficient VLSI architecture for DWT with low-storage. By revising the traditional lifting structure and employing time-multiplex data processing strategy to perform the second and third level of wavelet transformation by the same logic module, the usage of logic resource is reduced with no sacrifice on speed.Using a small amount of on-chip memory instead of off-chip memory to save certain parts of DWT coefficients and sending the coefficients in a specific sequence to entropy coder timely, the off-chip memory for storage of DWT coefficients is no longer required. The proposed VLSI architecture of DWT is already implemented on the Xilinx FPGA XC4VSX55, which can achieve a high performance, in terms of data throughput, reaching 95.91MPixels/s.

Key words: image processing, discrete wavelet transform(DWT), field programmable gate array(FPGA), very large scale integration(VLSI)

DONG Mingyan;LEI Jie;WANG Keyan;LI Yunsong. Highly efficient VLSI architecture for DWT with low-storage implementation[J].Journal of Xidian University, 2016, 43(2): 35-40.

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Highly efficient VLSI architecture for DWT with low-storage implementation

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