一种采用双层仲裁机制的新型总线仲裁器

doi:10.3969/j.issn.1001-2400.2017.01.003

Abstract

Abstract:

With the continuous increase in the complexity of the System-on-Chip(SoC), the growing demand for bandwidth and the unpredictable wire delay have made buses the bottleneck of SoC properties; researches on efficient bus arbiters, which play a decisive role in the properties of SoC, are of great significance. In view of the decisions made by arbiters are determined by arbitration algorithms which have little reliance on hardware structures, a software simulation platform is provided in this paper to verify the properties of arbiters, on which a novel arbiter based on the structure and trans-level judgment of the two-level arbiter is proposed. Simulation results show that the novel arbiter would reduce the standard deviation between the actual granted ratio and the required bandwidth ratio by 54.4％ and 50.8％ respectively in comparison with two traditional arbiters, indicating the approximation between granted ratio and the required bandwidth ratio.

Key words: system-on-chip (SoC), bus, arbiter, two-level arbitration, bandwidth ratio

LIU Lu;ZHOU Xiaofeng;ZHU Zhangming;ZHOU Duan;YANG Yintang. Novel bus arbiter with the two-level arbitration mechanism[J].Journal of Xidian University, 2017, 44(1): 12-17+105.

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Novel bus arbiter with the two-level arbitration mechanism

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