一种新型低存储二维离散小波变换架构

doi:10.3969/j.issn.1001-2400.2018.02.019

Abstract

Abstract:

Two-dimensional (2-D) Discrete Wavelet Transform (DWT) is a commonly used method in digital signal processing, image analysis and image compression. Due to its large amounts of computation, it is often implemented in a hardware circuit. In general, the hardware architectures have a large input RAM and large hardware resources, which restrict the improvement of system hardware efficiency. Therefore, a memory efficient 2-D DWT architecture based on the lifting scheme is proposed in this paper. The order of input data is adjusted, horizontal parallel scanning and data dislocation 3-input method are introduced in this work for reducing hardware resources and eliminating the off-chip RAM. For an image size of N×N, the total ram requirement of the proposed architecture is reduced to 9N bytes. The estimated hardware requirement shows that at least 8％ less transistor count-delay-product (TDP) can be saved compared with the existing architectures.

Key words: discrete wavelet transforms, very large scale integration, integrated circuit design, data dislocation method, off-chip random access memory less

GAO Jiaming;LIANG Yu;ZHANG Wei;LIU Yanyan. Memory efficient architecture for 2-D DWT[J].Journal of Xidian University, 2018, 45(2): 110-115.

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[1]	CHEN Chaowei;LIANG Yu;ZHANG Wei;BAO Na;LIU Yanyan. VLSI design of an efficient MQ encoder for JPEG2000 [J]. Journal of Xidian University, 2018, 45(3): 74-79+90.
[2]	JIA Qi;LIANG Yu;ZHANG Wei. Hardware efficient 2-D DWT architecture without off-chip RAM [J]. Journal of Xidian University, 2017, 44(4): 138-143.
[3]	DONG Mingyan;LEI Jie;WANG Keyan;LI Yunsong. Highly efficient VLSI architecture for DWT with low-storage implementation [J]. Journal of Xidian University, 2016, 43(2): 35-40.
[4]	LI Xiaofeng;FENG Dazheng;HU Shukai. Low power parallel VLSI architecture for spatially multiplexed MIMO detection [J]. J4, 2013, 40(6): 25-31+84.

Memory efficient architecture for 2-D DWT

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