Journal of Xidian University ›› 2019, Vol. 46 ›› Issue (1): 112-116.doi: 10.19665/j.issn1001-2400.2019.01.018

Previous Articles     Next Articles

Design scheme for an all-digital phase locked loop with a high performance

QU Bayi1,CHENG Teng1,YU Dongsong1,LI Zhiqi2,ZHOU Wei2,LI Shanshan1,LIU Lidong1   

  1. 1. School of Information Engineering, Chang’an University, Xi’an 710064;
    2. School of Mechano-electronic Engineering, Xidian Univ., Xi’an 710071, China;
  • Received:2018-08-30 Online:2019-02-20 Published:2019-03-05

Abstract:

Aiming at the fact that a complex scheme is needed when the two frequencies in the phase locked loop are close to each other or have an approximate integer multiple relationship and the traditional analog phase locked loop is unsuitable for integration and on chip implementation, an all-digital phase locked loop is proposed, which is mainly composed of analog to digital converters, an all-digital phase detector, a digital low pass filter and a digitally controlled oscillator. The analog to digital converters’ quantization errors have been greatly suppressed by using the clock cursor effect and digital edge effect and an all-digital phase locked loop with a high performance is achieved. Experiment indicates the correctness of the design scheme and shows that the proposed loop has characteristics of high precision and low noise.

Key words: digital phase locked loop, edge effect, all-digital phase detector, digitally controlled oscillator

CLC Number: 

  • TN911.8

Baidu
map