考虑电感效应和工艺波动影响的互连延时建模与计算

doi:10.3969/j.issn.1001-2400.2010.03.023

J4 ›› 2010, Vol. 37 ›› Issue (3): 513-519.doi: 10.3969/j.issn.1001-2400.2010.03.023

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Modeling and calculating of interconnect delay by considering the influence of inductance effect and process fluctuations

YANG Yang;CHAI Chang-chun;DONG Gang;YANG Yin-tang;LENG Peng

(Ministry of Education Key Lab. of Wide Band-Gap Semiconductor Materials and Devices, Xidian Univ., Xi'an 710071， China)

Received:2009-03-03 Online:2010-06-20 Published:2010-07-23
Contact: YANG Yang E-mail:999.002@163.com

Abstract

Abstract:

A statistical interconnect delay model considering the influence of inductance effect and process fluctuations is presented according to the improved equivalent Elmore delay, and the expressions for mean and standard deviation of interconnect delay are obtained. Calculated results indicate that the errors of the mean and standard deviation are less than 1.27％ and 5.23％ respectively in comparison with the results calculated by the widely used Monte Carlo method, and at the same time, the time elapsed for computing by using the proposed method is less than one ten-thousandth of that for 1000 computations by using the Monte Carlo method.

Key words: inductance, process fluctuations, interconnect delay, statistical model

YANG Yang;CHAI Chang-chun;DONG Gang;YANG Yin-tang;LENG Peng. Modeling and calculating of interconnect delay by considering the influence of inductance effect and process fluctuations[J].J4, 2010, 37(3): 513-519.

References

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Modeling and calculating of interconnect delay by considering the influence of inductance effect and process fluctuations

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