低功耗并行MIMO空间复用检测器的VLSI结构

doi:10.3969/j.issn.1001-2400.2013.06.005

Abstract

Abstract:

This paper proposes a novel maximum likelihood-like detection algorithm for the 2×2 MIMO wireless communication system. Only the second layer in the search tree needs to be verified exhaustively, and then the area determination strategy is applied to the first layer to figure out the hypothesis node and counter-hypothesis nodes without sorting the partial Euclidean distance for each layer, which reduces the complexity significantly and leads to parallel implementation. The regular VLSI architecture is designed according to the detection algorithm, and flexible parallelism can well control the throughput for versatile applications. The VLSI architecture is implemented with 40nm technology and constrained with the voltage of 1.08V and the clock frequency of 156MHz. The detector achieves 312Mbit/s throughput with the power dissipation of 23mW and the latency of 0.051ns .

Key words: sphere detection, spatially multiplexed multiple-input multiple-output, soft output, very large scale integration

LI Xiaofeng;FENG Dazheng;HU Shukai. Low power parallel VLSI architecture for spatially multiplexed MIMO detection[J].J4, 2013, 40(6): 25-31+84.

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Low power parallel VLSI architecture for spatially multiplexed MIMO detection

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