一种无片外存储的高性能二维DWT架构

doi:10.3969/j.issn.1001-2400.2017.04.024

Abstract

Abstract:

Two-dimensional(2-D) Discrete Wavelet Transform(DWT) is a commonly used image processing method. Due to its large amount of computation, it is often implemented in the hardware circuit to meet the need of high throughput. The existing hardware architectures have a large storage requirement for the input data. Therefore, a hardware efficient 2-D DWT architecture using the line-based and dual-scan method without multipliers is proposed. The total ram requirement of the proposed architecture is reduced to 10N bytes, while the off-chip RAM is not required. Besides, a Critical Path Delay(CPD) of one full-adder delay is achieved by using Canonic Sign Digit(CSD) multipliers. The estimated hardware requirement shows that the proposed architecture involves at least a 4％ smaller number of transistors and 33％ less transistor count-delay-product(TDP) than the existing architectures.

Key words: discrete wavelet transforms, very large scale integration, integrated circuit design, multiplier-less, off-chip random access memory less

JIA Qi;LIANG Yu;ZHANG Wei. Hardware efficient 2-D DWT architecture without off-chip RAM[J].Journal of Xidian University, 2017, 44(4): 138-143.

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[1]	CHEN Chaowei;LIANG Yu;ZHANG Wei;BAO Na;LIU Yanyan. VLSI design of an efficient MQ encoder for JPEG2000 [J]. Journal of Xidian University, 2018, 45(3): 74-79+90.
[2]	GAO Jiaming;LIANG Yu;ZHANG Wei;LIU Yanyan. Memory efficient architecture for 2-D DWT [J]. Journal of Xidian University, 2018, 45(2): 110-115.
[3]	DONG Mingyan;LEI Jie;WANG Keyan;LI Yunsong. Highly efficient VLSI architecture for DWT with low-storage implementation [J]. Journal of Xidian University, 2016, 43(2): 35-40.
[4]	LI Xiaofeng;FENG Dazheng;HU Shukai. Low power parallel VLSI architecture for spatially multiplexed MIMO detection [J]. J4, 2013, 40(6): 25-31+84.

Hardware efficient 2-D DWT architecture without off-chip RAM

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