Abstract: In order to investigate the easy latch-up and soft failure problem of on-chip integrated circuit electrostatic discharge (ESD) protection, a silicon controlled rectifier (SCR) embedded with the N-bridge and MOS (SCR-N-MOS) is proposed. The transmission line pulse test results show that the voltage snapback margin of the SCR-N-MOS is reduced by about 28.6% compared to the conventional N-bridge modified SCR. However, the leakage current of the SCR-N-MOS degrades gradually from 2.8×10^-7A to 1.7×10^-5A when the ESD transient current increases from 2.0A to 3.2A, resulting in soft failure. The technology computer aided design simulations of the SCR-N-MOS indicate that the lattice temperature increases  up to 1160.5K under an ESD current stress of 10^-4A. By optimizing the layout of the SCR-N-MOS and the metal wiring, the power density crowding effect is weakened and the leakage current can be decreased and maintained in the order of 10^-9A under the same stress. Therefore, the layout optimization method can effectively suppress the local overheating and improve the thermal stability of the on-chip integrated circuit ESD protection.

Key words: electrostatic discharge, silicon controlled rectifier, leakage characteristics, layout optimization, thermal effect