高精度电荷域ADC共模电荷误差前台校准电路

doi:10.3969/j.issn.1001-2400.2018.06.023

Abstract

Abstract: A mix-signal high precision common mode charge error calibration circuit is proposed. The calibration circuit can be used to compensate the common mode charge errors caused by the deviation of the charge transfer cutoff voltage of boosted charge transfer introduced by PVT variation, the variation of input common mode charge and the capacitor mismatch in the pipelined sub-stage circuit in the charge domain pipelined ADCs. Based on the proposed calibration circuit, a 14bit 210MS/s charge domain pipelined ADC is designed and realized in a 1P6M 0.18μm CMOS process. Test results show that the 14bit 210MS/s ADC achieves the signal-to-noise ratio of 71.5dBFS and the spurious free dynamic range of 85.4dB, with 30.1MHz input single tone signal at 210MS/s, while the ADC core consumes the power of 205mW and occupies an area of 3.2mm².

Key words: pipelined analog-to-digital converter, charge-domain, fore-ground calibration, low power, common-mode charge

CLC Number:

TN432

CHEN Zhenhai, WEI Jinghe, YU Zongguang, SU Xiaobo, XUE Yan, ZHANG Hong. High precision common mode charge error fore-ground calibration circuit for the charge-domain ADC[J].Journal of Xidian University, 2018, 45(6): 137-143+149.

References ［14］

［1］	陈珍海, 于宗光, 李现坤, 等. 用于16bit 100MS/s ADC的高精度参考电压产生电路［J］. 西安电子科技大学学报, 2017, 44(3): 127-132 .<br />
	CHEN Zhenhai, YU Zongguang, LI Xiankun，et al. High Precision Voltage Reference Generator for 16-bit 100MS/s ADC ［J］. Journal of Xidian University, 2017, 44(3): 127-132.<br />
［2］	MANAR E, LI X P, SHIGENOBU K, et al. A 90dB SFDR 14-b 500MS/s BiCMOS Switched-current Pipelined ADC［C］//Proceedings of the 2015 International Solid-State Circuits Conference. Piscataway: IEEE, 2015: 286-287.<br />
［3］	LI W T, LI F L , YANG C Y, et al. An 85mW 14-bit 150MS/s Pipelined ADC with a Merged First and Second MDAC［J］. China Communications, 2015, 12(5): 14-22.<br />
［4］	ALI A M A, DINC H, BHORASKAR P, et al. A 14Bit 1GS/s RF Sampling Pipelined ADC with Background Calibration［J］. IEEE Journal of Solid-State Circuits, 2014, 49(12): 2857-2867.<br />
［5］	ALI A M A, DINC H, BHORASKAR P, et al. A 14-bit 2. 5GS/s and 5GS/s RF Sampling ADC with Background Calibration and Dither［C］//2016 IEEE Symposium on VLSI Circuits, Digest of Technical Papers. Piscataway: IEEE, 2016: 7573537.<br />
［6］	WU J F, CHOU A, LI T W, et al. A 4GS/s 13b Pipelined ADC with Capacitor and Amplifier Sharing in 16nm CMOS［C］//Proceedings of the 2016 IEEE International Solid-State Circuits Conference. Piscataway: IEEE, 2016: 466-467.<br />
［7］	ANTHONY M, KOHLER E, KURTZE J, et. al. A Process-scalable Low-power Charge-domain 13-bit Pipeline ADC［C］//2008 IEEE Symposium on VLSI Circuits, Digest of Technical Papers. Piscataway: IEEE, 2008: 212-213.<br />
［8］	黄嵩人, 陈珍海, 张鸿, 等. 用于电荷域流水线ADC的1. 5位子级电路［J］. 西安电子科技大学学报, 2016, 43(6): 170-175.<br />
	HUANG Songren, CHEN Zhenhai, ZHANG Hong，et al. 1. 5bit Substage Circuit for Charge Domain Pipelined ADCs［J］. Journal of Xidian University, 2016, 43(6): 170-175.<br />
［9］	CHEN Z H, YU Z G, HUANG S R, et al. A PVT Insensitive Boosted Charge Transfer for High Speed Charge-domain Pipelined ADCs［J］. IEICE Electronics Express, 2012, 9(6): 565-571.<br />
［10］	CHEN Z H, HUANG S R, ZHANG H, et. al. A 27-mW 10-bit 125-MSPS Charge-domain Pipelined ADC with PVT Insensitive Boosted Charge Transfer［J］. Journal of Semiconductors, 2013, 34(3): 035009.<br />
［11］	HUANG S R, ZHANG H, CHEN Z H, et. al. A 10-bit 250MSPS Charge-domain Pipelined ADC with Replica Controlled PVT Insensitive BCT Circuit［J］. Journal of Semiconductors, 2015, 36(5): 055012.<br />
［12］	陈珍海, 魏敬和, 苏小波, 等. 低功耗时间交织12位500MS/s电荷域ADC［J］. 西安电子科技大学学报, 2017, 44(6): 119-126.<br />
	CHEN Zhenhai, WEI Jinghe, SU Xiaobo, et al. Low Power Time-interleaved 12bit 500MS/s Charge Domain ADC［J］. Journal of Xidian University, 2017, 44(6): 119-126.<br />
［13］	ZHANG Y W, CHEN C X, YU B, et. al. A 14-bit 200-MS/s Time-interleaved ADC with Sample-time Error Calibration［J］. Journal of Semiconductors, 2012, 33(10): 105010.<br />
［14］	ZHENG X Q, WANG Z J, LI F L, et al. A 14-bit 250MS/s Pipelined ADC with a Merged First and Second MDAC［J］. IEEE Transactions on Circuits and Systems—Ⅰ: Regular Papers, 2016, 63(9): 1381-1392.<br />
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[1]	CHEN Diping, YING Tao, DONG Gang. Design of a low-power low-temperature-drift LDO regulator in mobile chips [J]. Journal of Xidian University, 2018, 45(6): 57-62.
[2]	CAI Jiangzheng;HEI Yong;YUAN Jia;CHEN Liming. Near-threshold non-precharged SRAM [J]. Journal of Xidian University, 2018, 45(1): 106-111.
[3]	CHEN Zhenhai;WEI Jinghe;SU Xiaobo;ZOU Jiaxuan;ZHANG Hong;YU Zongguang. Low power time-interleaved 12-bit 500MS／s charge-domain ADC [J]. Journal of Xidian University, 2017, 44(6): 109-115+137.
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[5]	CHEN Zhenhai;YU Zongguang;LI Xiankun;WEI Jinghe;HUANG Songren;SU Xiaobo. High precision voltage reference generator for 16-bit 100MS/s ADC [J]. Journal of Xidian University, 2017, 44(3): 127-132+180.
[6]	MENG Fanzhen;LIU Hong;WANG Mingliang;LIN Shuiyang;TIAN Tong. Design of the low power wake-up receiver for internet of things communication [J]. Journal of Xidian University, 2017, 44(2): 95-100.
[7]	HUANG Songren;CHEN Zhenhai;ZHANG Hong;LI Xue;QIAN Hongwen;YU Zongguang. 1.5bit substage circuit for charge domain pipelined ADCs [J]. Journal of Xidian University, 2016, 43(6): 170-175.
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[9]	DONG Siwan;ZHU Zhangming;LIU Minjie;YANG Yintang. Optimum design of the MDAC circuit for the 8bit 80MS/s pipelined A/D converter [J]. J4, 2016, 43(1): 162-166+172.
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High precision common mode charge error fore-ground calibration circuit for the charge-domain ADC

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