一种高性能可重构深度卷积神经网络加速器

doi:10.19665/j.issn1001-2400.2019.03.020

Abstract

Abstract:

In deep convolutional neural networks,the diversity of channel sizes and kernel sizes makes it difficult for existing accelerators to achieve efficient calculations. Therefore, based on the biological brain neuron mechanism, a deep convolutional neural network accelerator is proposed which can provide not only multiple clustering methods for brain-like neurons and link organization among brain-like neurons towards different channel sizes, but also three mapping methods for different convolution kernel sizes. The accelerator implements efficient reuse of local memory data, which greatly reduces the amount of data movement and improves the computing performance. Tested by the object classification network and object detection network, the accelerator's computational performance is 498.6 GOPS and 571.3 GOPS, respectively; the energy efficiency is 582.0 GOPS/W and 651.7 GOPS/W, respectively.

Key words: deep neural networks, accelerator, reconfigurable architecture, high performance, very large scale integrated circuit

CLC Number:

QIAO Ruixiu,CHEN Gang,GONG Guoliang,LU Huaxiang. High performance reconfigurable accelerator for deep convolutional neural networks[J].Journal of Xidian University, 2019, 46(3): 130-139.

Figures/Tables 13

References 18

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卷积映射		3×3卷积	1×1卷积及全连接	7×7卷积
PE计算方式		按窗口计算	多输入通道累加	按行计算
PE利用率/%		100	100	87.5
可实现复用关系	局部存储区内数据分时复用	PR,WR	IR	PR,WR
	局部存储区间共享总线数据	IR	IR	PR,IR
F_i	分时复用产生的减少比(F_ia)	(1/9)·(1/T_o)	1/T_o	(1/7)·(1/T_o)
	总线共享产生的减少比(F_ib)	1/P_o	1/P_o	1/P_o
F_p	分时复用产生的减少比(F_pa)	1	1/T_i	1
	总线共享产生的减少比(F_pb)	1/P_i	1/P_i	1/P_i

性能参数指标	参数值
工艺技术	TSMC 28nm HPC
芯片尺寸/mm²	3.814× 4.034
逻辑门数	2 290×10⁴
片上SRAM/MB	2.16
PE数量	512
供电电压/V	Core: 0.810.99
	I/O: 1.8
时钟频率/GHz	1
计算峰值/(次·秒^-1)	1.024×10¹²
精度	16 位定点
平均功率/mW	877

layers	conv1	conv4	conv7	conv16	conv17	fc1
输入[N, R, C]	[3,448,448]	[128,56,56]	[512,28,28]	[512,28,28]	[1 024,14,14]	[1 024,7,7]
权重[M, N, k, s]	[64,3,7,2]	[256,128,3,1]	[256,512,1,1]	[1 024,512,3,1]	[512,1 024,1,1]	[512,1 024,7,1]
输出[M, R, C]	[64,112,112]	[256,56,56]	[256,28,28]	[1 024,14,14]	[512,14,14]	[512,1,1]
池化层(有/无)	有	无	无	有	无	无
T_i	1	1	4	1	4	1
T_o	8	6	16	6	16	8
P_i	3	128	128	128	256	32
P_o	8	4	4	2	2	2
特征图重传次数	1	11	4	86	16	32
PE利用率/%	65.625	100	100	100	100	87.5
输入缓存访问量/B	1 905 152	9 205 760	3 211 264	125 829 120	6 422 528	3 211 264
中间结果访问量/B	0	0	0	19 267 584	0	126 976
F_i/%	0.15	0.50	1.56	1.70	3.13	6.25
F_p	0	0	0	0.59	0	3.03

layers	conv1	conv2	conv3	conv4	conv5	conv6	conv7	conv8	conv9
运行时间	1.660	3.061	0.218	2.117	0.510	2.143	0.405	2.686	0.405
layers	conv10	conv11	conv12	conv13	conv14	conv15	conv16	conv17	conv18
运行时间	2.686	0.405	2.686	0.405	2.686	0.811	22.805	0.807	2.046
layers	conv19	conv20	conv21	conv22	conv23	conv24	fc1	fc2	fc3	总计
运行时间	0.807	2.046	4.091	2.167	1.183	1.183	0.480	0.015	0.202	60.717

layers	conv1_1	conv1_2	conv2_1	conv2_2	conv3_1	conv3_2	conv3_3	conv4_1
运行时间	2.067	4.993	2.087	4.993	2.162	6.201	20.239	2.682
layers	conv4_2	conv4_3	conv5_1	conv5_2	conv5_3	fc1	fc2	fc3	总计
运行时间	5.367	11.400	1.038	1.060	1.964	1.921	0.562	0.136	68.872

High performance reconfigurable accelerator for deep convolutional neural networks

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Figures/Tables 13

References 18

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名称	NVIDA GPU	FPGA^[18]	Eyeriss^[11]	DNA^[12]	CASSANN-X
工艺技术	GTX TIAN X	Xilinx XC7Z045	ASIC 65 nm	ASIC 65 nm	ASIC 28 nm
PE数量			168	512	512
频率/MHz	1 582	150	200	200	1 000
SRAM			108kB	280kB	2.1MB
DCNN	YOLO	VGG16	VGG16	VGG19	YOLO	VGG16
性能/(10⁹次·秒^-1)	1 456.0	136.97	21.4	194.4	571.3	498.6
功率/W	250	9.630	0.236	0.479	0.877	0.857
能效/(10⁹次·秒^-1·瓦^-1)	5.8	14.22	166.2	406.2	651.7	582.0

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