Abstract:

The Network-on-Chip Router is the key component of multi/many-core processors.In this paper,firstly the schematic architectures of the synchronous First-Input-First-Output (FIFO) buffer and asynchronous FIFO buffer are reviewed with their latencies addressed.Then the architectures of the Network-on-Chip (NoC) and its router are introduced.With the previous foundations,an optimized clock tree distribution scheme,as well as the NoC router implementation under this clock tree distribution scheme,are proposed.With this novel clock tree optimization,the latency of the NoC is greatly reduced.In addition,in order to decrease the area of the register based FIFO,the latch based FIFO is proposed.Single tick latch writing is ensured.And sharing multiple FIFOs is proposed.The proposed techniques are especially useful for embedded low-power many-core processors.

Key words: first-input-first-output, network-on-chip, router